220 lines
12 KiB
YAML
220 lines
12 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra238 Pinmux Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra238-pinmux
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reg:
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maxItems: 1
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patternProperties:
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"^pinmux(-[a-z0-9-]+)?$":
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type: object
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# pin groups
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additionalProperties:
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$ref: nvidia,tegra238-pinmux-common.yaml
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properties:
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nvidia,pins:
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items:
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enum: [ gpu_pwr_req_pa0, gp_pwm5_pa1, gp_pwm6_pa2, spi3_sck_pa3,
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spi3_miso_pa4, spi3_mosi_pa5, spi3_cs0_pa6, spi3_cs1_pa7,
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spi1_sck_pb0, spi1_miso_pb1, spi1_mosi_pb2, spi1_cs0_pb3,
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spi1_cs1_pb4, pwr_i2c_scl_pc0, pwr_i2c_sda_pc1,
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extperiph1_clk_pc2, extperiph2_clk_pc3, cam_i2c_scl_pc4,
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cam_i2c_sda_pc5, soc_gpio23_pc6, soc_gpio24_pc7,
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soc_gpio27_pd0, soc_gpio55_pd1, soc_gpio29_pd2,
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soc_gpio33_pd3, soc_gpio32_pd4, soc_gpio35_pd5,
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soc_gpio37_pd6, soc_gpio56_pd7, uart1_tx_pe0,
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uart1_rx_pe1, uart1_rts_pe2, uart1_cts_pe3,
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soc_gpio13_pf0, soc_gpio14_pf1, soc_gpio15_pf2,
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soc_gpio16_pf3, soc_gpio17_pf4, soc_gpio18_pf5,
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soc_gpio20_pf6, soc_gpio21_pf7, soc_gpio22_pg0,
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soc_gpio06_pg1, uart4_tx_pg2, uart4_rx_pg3,
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uart4_rts_pg4, uart4_cts_pg5, soc_gpio41_pg6,
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soc_gpio42_pg7, soc_gpio43_ph0, soc_gpio44_ph1,
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gen1_i2c_scl_ph2, gen1_i2c_sda_ph3, cpu_pwr_req_ph4,
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soc_gpio07_ph5, dap3_clk_pj0, dap3_dout_pj1,
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dap3_din_pj2, dap3_fs_pj3, soc_gpio57_pj4,
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soc_gpio58_pj5, soc_gpio59_pj6, soc_gpio60_pj7,
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soc_gpio45_pk0, soc_gpio46_pk1, soc_gpio47_pk2,
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soc_gpio48_pk3, qspi0_sck_pl0, qspi0_io0_pl1,
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qspi0_io1_pl2, qspi0_cs_n_pl3, soc_gpio152_pl4,
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soc_gpio153_pl5, soc_gpio154_pl6, soc_gpio155_pl7,
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soc_gpio156_pm0, soc_gpio157_pm1, soc_gpio158_pm2,
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soc_gpio159_pm3, soc_gpio160_pm4, soc_gpio161_pm5,
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soc_gpio162_pm6, uart7_tx_pm7, uart7_rx_pn0,
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uart7_rts_pn1, uart7_cts_pn2, soc_gpio167_pp0,
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soc_gpio168_pp1, soc_gpio169_pp2, soc_gpio170_pp3,
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dap4_sclk_pp4, dap4_dout_pp5, dap4_din_pp6, dap4_fs_pp7,
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soc_gpio171_pq0, soc_gpio172_pq1, soc_gpio173_pq2,
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soc_gpio61_pr0, soc_gpio62_pr1, soc_gpio63_pr2,
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soc_gpio64_pr3, soc_gpio65_pr4, soc_gpio66_pr5,
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soc_gpio67_pr6, soc_gpio68_pr7, gen4_i2c_scl_ps0,
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gen4_i2c_sda_ps1, soc_gpio75_ps2, gen7_i2c_scl_ps3,
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gen7_i2c_sda_ps4, soc_gpio78_ps5, gen9_i2c_scl_ps6,
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gen9_i2c_sda_ps7, soc_gpio81_pt0, soc_gpio36_pt1,
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soc_gpio53_pt2, soc_gpio38_pt3, soc_gpio40_pt4,
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soc_gpio34_pt5, usb_vbus_en0_pt6, usb_vbus_en1_pt7,
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sdmmc1_clk_pu0, sdmmc1_cmd_pu1, sdmmc1_dat0_pu2,
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sdmmc1_dat1_pu3, sdmmc1_dat2_pu4, sdmmc1_dat3_pu5,
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ufs0_ref_clk_pv0, ufs0_rst_n_pv1, pex_l0_clkreq_n_pw0,
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pex_l0_rst_n_pw1, pex_l1_clkreq_n_pw2,
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pex_l1_rst_n_pw3, pex_l2_clkreq_n_pw4,
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pex_l2_rst_n_pw5, pex_l3_clkreq_n_pw6,
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pex_l3_rst_n_pw7, pex_wake_n_px0, dp_aux_ch0_hpd_px1,
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bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
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pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
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soc_gpio25_paa6, soc_gpio26_paa7, hdmi_cec_pbb0,
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spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
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spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
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uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
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gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3,
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dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6,
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pwm2_pdd7, pwm3_pee0, pwm7_pee1, soc_gpio49_pee2,
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soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5,
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soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2,
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soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5,
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soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0,
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soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3,
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uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6,
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uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1,
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uart5_cts_phh2, soc_gpio86_phh3, sdmmc1_comp,
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# drive groups
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drive_soc_gpio36_pt1, drive_soc_gpio53_pt2,
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drive_soc_gpio38_pt3, drive_soc_gpio40_pt4,
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drive_soc_gpio75_ps2, drive_soc_gpio81_pt0,
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drive_soc_gpio78_ps5, drive_soc_gpio34_pt5,
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drive_gen7_i2c_scl_ps3, drive_gen7_i2c_sda_ps4,
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drive_gen4_i2c_sda_ps1, drive_gen4_i2c_scl_ps0,
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drive_gen9_i2c_sda_ps7, drive_gen9_i2c_scl_ps6,
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drive_usb_vbus_en0_pt6, drive_usb_vbus_en1_pt7,
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drive_soc_gpio61_pr0, drive_soc_gpio62_pr1,
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drive_soc_gpio63_pr2, drive_soc_gpio64_pr3,
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drive_soc_gpio65_pr4, drive_soc_gpio66_pr5,
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drive_soc_gpio67_pr6, drive_soc_gpio68_pr7,
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drive_spi3_miso_pa4, drive_spi1_cs0_pb3,
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drive_spi3_cs0_pa6, drive_spi1_miso_pb1,
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drive_spi3_cs1_pa7, drive_spi1_sck_pb0,
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drive_spi3_sck_pa3, drive_spi1_cs1_pb4,
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drive_spi1_mosi_pb2, drive_spi3_mosi_pa5,
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drive_gpu_pwr_req_pa0, drive_gp_pwm5_pa1,
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drive_gp_pwm6_pa2, drive_extperiph2_clk_pc3,
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drive_extperiph1_clk_pc2, drive_cam_i2c_sda_pc5,
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drive_cam_i2c_scl_pc4, drive_soc_gpio23_pc6,
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drive_soc_gpio24_pc7, drive_soc_gpio27_pd0,
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drive_soc_gpio29_pd2, drive_soc_gpio32_pd4,
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drive_soc_gpio33_pd3, drive_soc_gpio35_pd5,
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drive_soc_gpio37_pd6, drive_soc_gpio56_pd7,
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drive_soc_gpio55_pd1, drive_uart1_cts_pe3,
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drive_uart1_rts_pe2, drive_uart1_rx_pe1,
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drive_uart1_tx_pe0, drive_pwr_i2c_scl_pc0,
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drive_pwr_i2c_sda_pc1, drive_cpu_pwr_req_ph4,
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drive_uart4_cts_pg5, drive_uart4_rts_pg4,
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drive_uart4_rx_pg3, drive_uart4_tx_pg2,
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drive_gen1_i2c_scl_ph2, drive_gen1_i2c_sda_ph3,
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drive_soc_gpio20_pf6, drive_soc_gpio21_pf7,
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drive_soc_gpio22_pg0, drive_soc_gpio13_pf0,
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drive_soc_gpio14_pf1, drive_soc_gpio15_pf2,
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drive_soc_gpio16_pf3, drive_soc_gpio17_pf4,
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drive_soc_gpio18_pf5, drive_soc_gpio41_pg6,
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drive_soc_gpio42_pg7, drive_soc_gpio43_ph0,
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drive_soc_gpio44_ph1, drive_soc_gpio06_pg1,
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drive_soc_gpio07_ph5, drive_dap4_sclk_pp4,
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drive_dap4_dout_pp5, drive_dap4_din_pp6,
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drive_dap4_fs_pp7, drive_soc_gpio167_pp0,
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drive_soc_gpio168_pp1, drive_soc_gpio169_pp2,
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drive_soc_gpio170_pp3, drive_soc_gpio171_pq0,
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drive_soc_gpio172_pq1, drive_soc_gpio173_pq2,
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drive_soc_gpio45_pk0, drive_soc_gpio46_pk1,
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drive_soc_gpio47_pk2, drive_soc_gpio48_pk3,
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drive_soc_gpio57_pj4, drive_soc_gpio58_pj5,
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drive_soc_gpio59_pj6, drive_soc_gpio60_pj7,
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drive_dap3_fs_pj3, drive_dap3_clk_pj0,
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drive_dap3_din_pj2, drive_dap3_dout_pj1,
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drive_pex_l2_clkreq_n_pw4, drive_pex_wake_n_px0,
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drive_pex_l1_clkreq_n_pw2, drive_pex_l1_rst_n_pw3,
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drive_pex_l0_clkreq_n_pw0, drive_pex_l0_rst_n_pw1,
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drive_pex_l2_rst_n_pw5, drive_pex_l3_clkreq_n_pw6,
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drive_pex_l3_rst_n_pw7, drive_dp_aux_ch0_hpd_px1,
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drive_qspi0_io0_pl1, drive_qspi0_io1_pl2,
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drive_qspi0_sck_pl0, drive_qspi0_cs_n_pl3,
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drive_soc_gpio156_pm0, drive_soc_gpio155_pl7,
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drive_soc_gpio160_pm4, drive_soc_gpio154_pl6,
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drive_soc_gpio152_pl4, drive_soc_gpio153_pl5,
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drive_soc_gpio161_pm5, drive_soc_gpio162_pm6,
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drive_soc_gpio159_pm3, drive_soc_gpio157_pm1,
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drive_soc_gpio158_pm2, drive_uart7_cts_pn2,
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drive_uart7_rts_pn1, drive_uart7_tx_pm7,
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drive_uart7_rx_pn0, drive_sdmmc1_clk_pu0,
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drive_sdmmc1_cmd_pu1, drive_sdmmc1_dat3_pu5,
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drive_sdmmc1_dat2_pu4, drive_sdmmc1_dat1_pu3,
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drive_sdmmc1_dat0_pu2, drive_ufs0_rst_n_pv1,
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drive_ufs0_ref_clk_pv0, drive_batt_oc_paa4,
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drive_bootv_ctl_n_paa0, drive_vcomp_alert_paa2,
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drive_hdmi_cec_pbb0, drive_touch_clk_pdd3,
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drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
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drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
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drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
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drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
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drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
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drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,
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drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,
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drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,
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drive_soc_gpio00_paa1, drive_soc_gpio19_pdd6,
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drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,
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drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,
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drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,
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drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,
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drive_soc_gpio04_paa5, drive_soc_gpio85_pgg6,
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drive_soc_gpio69_pff0, drive_soc_gpio25_paa6,
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drive_soc_gpio26_paa7, drive_uart5_tx_pgg7,
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drive_uart5_rx_phh0, drive_uart2_tx_pgg2,
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drive_uart2_rx_pgg3, drive_uart2_cts_pgg5,
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drive_uart2_rts_pgg4, drive_uart5_cts_phh2,
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drive_uart5_rts_phh1, drive_pwm7_pee1,
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drive_pwm2_pdd7, drive_pwm3_pee0, drive_pwm1_paa3,
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drive_spi2_cs1_pcc4, drive_dmic1_clk_pdd4,
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drive_dmic1_dat_pdd5, drive_sdmmc1_comp ]
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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pinmux@2430000 {
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compatible = "nvidia,tegra238-pinmux";
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reg = <0x2430000 0x17000>;
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pinctrl-names = "pex_rst";
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pinctrl-0 = <&pex_rst_c5_out_state>;
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pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
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pexrst {
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nvidia,pins = "pex_l3_rst_n_pw7";
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nvidia,schmitt = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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nvidia,io-hv = <TEGRA_PIN_ENABLE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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};
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};
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};
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...
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