79 lines
2.8 KiB
YAML
79 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra264 UPHY Pinmux Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra264-pinmux-uphy
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reg:
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maxItems: 1
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patternProperties:
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"^pinmux(-[a-z0-9-]+)?$":
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type: object
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# pin groups
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additionalProperties:
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$ref: nvidia,tegra264-pinmux-common.yaml
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properties:
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nvidia,pins:
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items:
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enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1,
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pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4,
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eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3,
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eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0,
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pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3,
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pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5,
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sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6,
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soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3,
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ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0,
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drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1,
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drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3,
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drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1,
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drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6,
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drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0,
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drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2,
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drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2,
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drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5,
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drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1,
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drive_soc_gpio113_pb6, drive_soc_gpio114_pb7,
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drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2,
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drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ]
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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pinmux@82e0000 {
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compatible = "nvidia,tegra264-pinmux-uphy";
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reg = <0x82e0000 0x4000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_default>;
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pinmux_default: pinmux-default {
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pex {
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nvidia,pins = "pex_l1_rst_n_pb1";
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nvidia,pull = <TEGRA_PIN_PULL_NONE>;
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nvidia,tristate = <TEGRA_PIN_DISABLE>;
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nvidia,enable-input = <TEGRA_PIN_ENABLE>;
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};
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};
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};
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