47 lines
1.1 KiB
C
47 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2026 Cix Technology Group Co., Ltd.
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*/
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#ifndef __SKY1_POWER_H__
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#define __SKY1_POWER_H__
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/* The Rich OS need flow the macro */
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#define SKY1_PD_AUDIO 0
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#define SKY1_PD_PCIE_CTRL0 1
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#define SKY1_PD_PCIE_DUMMY 2
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#define SKY1_PD_PCIEHUB 3
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#define SKY1_PD_MMHUB 4
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#define SKY1_PD_MMHUB_SMMU 5
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#define SKY1_PD_DPU0 6
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#define SKY1_PD_DPU1 7
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#define SKY1_PD_DPU2 8
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#define SKY1_PD_DPU3 9
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#define SKY1_PD_DPU4 10
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#define SKY1_PD_VPU_TOP 11
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#define SKY1_PD_VPU_CORE0 12
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#define SKY1_PD_VPU_CORE1 13
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#define SKY1_PD_VPU_CORE2 14
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#define SKY1_PD_VPU_CORE3 15
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#define SKY1_PD_NPU_CORE0 16
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#define SKY1_PD_NPU_CORE1 17
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#define SKY1_PD_NPU_CORE2 18
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#define SKY1_PD_NPU_TOP 19
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#define SKY1_PD_ISP0 20
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#define SKY1_PD_GPU 21
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#define SKY1_PERF_GPU_CORE 0
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#define SKY1_PERF_GPU_TOP 1
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#define SKY1_PERF_CPU_L 2
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#define SKY1_PERF_CPU_B0 3
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#define SKY1_PERF_CPU_B1 4
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#define SKY1_PERF_CPU_M0 5
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#define SKY1_PERF_CPU_M1 6
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#define SKY1_PERF_DSU 7
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#define SKY1_PERF_NPU 8
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#define SKY1_PERF_VPU 9
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#define SKY1_PERF_CI700 10
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#define SKY1_PERF_NI700 11
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#endif
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