798 lines
19 KiB
Devicetree
798 lines
19 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include "imx8mp.dtsi"
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/ {
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model = "NXP i.MX8MPlus FRDM board";
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compatible = "fsl,imx8mp-frdm", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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gpio-leds {
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compatible = "gpio-leds";
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led-0 {
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label = "red";
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gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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led-1 {
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label = "green";
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gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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led-2 {
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label = "blue";
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gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>;
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default-state = "off";
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};
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0xc0000000>,
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<0x1 0x00000000 0 0x40000000>;
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};
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native-hdmi-connector {
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compatible = "hdmi-connector";
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label = "HDMI OUT";
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type = "a";
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port {
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hdmi_in: endpoint {
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remote-endpoint = <&hdmi_tx_out>;
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};
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};
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};
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reg_usdhc2_vmmc: regulator-sd {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_vbus: regulator-vbus {
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compatible = "regulator-fixed";
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regulator-name = "USB_VBUS";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc1_vmmc: regulator-wifi-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "WLAN_EN";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>;
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/*
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* IW612 wifi chip needs more delay than other wifi chips to complete
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* the host interface initialization after power up, otherwise the
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* internal state of IW612 may be unstable, resulting in the failure of
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* the SDIO3.0 switch voltage.
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*/
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enable-active-high;
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startup-delay-us = <20000>;
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};
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reg_usdhc1_vqmmc: regulator-wifi-vqmmc {
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compatible = "regulator-fixed";
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regulator-name = "regulator-wifi-vqmmc";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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enable-active-high;
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};
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sdio_pwrseq: usdhc1-pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
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};
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};
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&A53_0 {
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cpu-supply = <®_arm>;
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};
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&A53_1 {
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cpu-supply = <®_arm>;
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};
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&A53_2 {
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cpu-supply = <®_arm>;
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};
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&A53_3 {
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cpu-supply = <®_arm>;
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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snps,force_thresh_dma_mode;
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snps,mtl-tx-config = <&mtl_tx_setup>;
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snps,mtl-rx-config = <&mtl_rx_setup>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos_phy>;
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reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <80000>;
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};
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};
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mtl_tx_setup: tx-queues-config {
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snps,tx-queues-to-use = <5>;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,priority = <0xf0>;
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};
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};
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mtl_rx_setup: rx-queues-config {
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snps,rx-queues-to-use = <5>;
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snps,rx-sched-sp;
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queue0 {
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snps,dcb-algorithm;
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snps,priority = <0x1>;
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snps,map-to-dma-channel = <0>;
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};
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queue1 {
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snps,dcb-algorithm;
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snps,priority = <0x2>;
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snps,map-to-dma-channel = <1>;
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};
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queue2 {
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snps,dcb-algorithm;
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snps,priority = <0x4>;
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snps,map-to-dma-channel = <2>;
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};
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queue3 {
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snps,dcb-algorithm;
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snps,priority = <0x8>;
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snps,map-to-dma-channel = <3>;
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};
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queue4 {
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snps,dcb-algorithm;
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snps,priority = <0xf0>;
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snps,map-to-dma-channel = <4>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy>;
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eee-broken-1000t;
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reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <80000>;
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realtek,aldps-enable;
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realtek,clkout-disable;
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};
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};
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};
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&hdmi_pvi {
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status = "okay";
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};
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&hdmi_tx {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hdmi>;
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status = "okay";
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ports {
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port@1 {
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hdmi_tx_out: endpoint {
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remote-endpoint = <&hdmi_in>;
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};
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};
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};
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};
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&hdmi_tx_phy {
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9450c";
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reg = <0x25>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <720000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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reg_arm: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <720000>;
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regulator-max-microvolt = <1025000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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};
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BUCK4 {
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regulator-name = "BUCK4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3600000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_buck5: BUCK5 {
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regulator-name = "BUCK5";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <1045000>;
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regulator-max-microvolt = <1155000>;
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regulator-boot-on;
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regulator-always-on;
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};
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LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1650000>;
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regulator-max-microvolt = <1950000>;
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regulator-boot-on;
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regulator-always-on;
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};
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LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <1710000>;
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regulator-max-microvolt = <1890000>;
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regulator-boot-on;
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regulator-always-on;
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};
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LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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pcal6416_0: gpio@20 {
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compatible = "nxp,pcal6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcal6416_0_int>;
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interrupt-parent = <&gpio3>;
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interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
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gpio-line-names = "CSI1_nRST",
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"CSI2_nRST",
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"DSI_CTP_RST",
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"EXT_PWREN1",
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"CAN_STBY",
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"EXP_P0_5",
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"EXP_P0_6",
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"P0_7",
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"LVDS0_BLT_EN",
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"LVDS1_BLT_EN",
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"LVDS0_CTP_RST",
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"LVDS1_CTP_RST",
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"SPK_PWREN",
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"RLED_GPIO",
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"GLED_GPIO",
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"BLED_GPIO";
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};
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pcal6416_1: gpio@21 {
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compatible = "nxp,pcal6416";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcal6416_1_int>;
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interrupt-parent = <&gpio2>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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gpio-line-names = "P0_0",
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"P0_1",
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"AUD_nINT",
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"RTC_nINTA",
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"USB1_SS_SEL",
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"USB2_PWR_EN",
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"SPI_EXP_SEL",
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"P0_7",
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"W2_HOST_WAKE_SD_3V3",
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"W2_HOST_WAKE_BT_3V3",
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"EXP_WIFI_BT_PDN_3V3",
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"EXP_BT_RST_3V3",
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"W2_RST_IND_3V3",
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"SPI_nINT_3V3",
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"KEYM_PCIE_nWAKE",
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"P1_7";
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&i2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&lcdif3 {
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status = "okay";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clk IMX8MP_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
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uart-has-rtscts;
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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&usb3_phy0 {
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status = "okay";
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};
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&usb3_phy1 {
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vbus-supply = <®_usb_vbus>;
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status = "okay";
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};
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&usb_dwc3_1 {
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dr_mode = "host";
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status = "okay";
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};
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&usdhc1 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
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assigned-clock-rates = <200000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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mmc-pwrseq = <&sdio_pwrseq>;
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vmmc-supply = <®_usdhc1_vmmc>;
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vqmmc-supply = <®_usdhc1_vqmmc>;
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bus-width = <4>;
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non-removable;
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no-sd;
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no-mmc;
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status = "okay";
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};
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&usdhc2 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&usdhc3 {
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assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
|
|
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
|
|
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
|
|
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
|
|
>;
|
|
};
|
|
|
|
pinctrl_eqos_phy: eqosphygrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec: fecgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
|
|
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
|
|
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
|
|
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
|
|
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
|
|
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
|
|
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
|
|
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
|
|
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
|
|
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
|
|
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
|
|
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
|
|
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
|
|
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec_phy: fecphygrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
|
|
>;
|
|
};
|
|
|
|
pinctrl_hdmi: hdmigrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
|
|
>;
|
|
};
|
|
|
|
pinctrl_hog: hoggrp {
|
|
fsl,pins = <
|
|
/* Pin might be required by multiple drivers
|
|
* (e. g. HDMI Audio and HDMI TX)
|
|
*/
|
|
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
|
|
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
|
|
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
|
|
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT)
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
|
|
(MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcal6416_0_int: pcal6416-0-int-grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16
|
|
(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcal6416_1_int: pcal6416-1-int-grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11
|
|
(MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
|
|
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
|
|
(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
|
|
(MX8MP_FSEL_FAST | MX8MP_PULL_UP |
|
|
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 MX8MP_USDHC_DATA_DEFAULT
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
|
|
(MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
|
|
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST |
|
|
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
|
|
(MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
|
|
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST |
|
|
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK
|
|
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST |
|
|
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD
|
|
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP |
|
|
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7
|
|
(MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT)
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE
|
|
(MX8MP_DSE_X6 | MX8MP_FSEL_FAST |
|
|
MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE)
|
|
>;
|
|
};
|
|
};
|