481 lines
11 KiB
Devicetree
481 lines
11 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Variscite Sonata carrier board for DART-MX91
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*
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* Link: https://variscite.com/carrier-boards/sonata-board/
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*
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* Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
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*
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*/
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/dts-v1/;
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#include "imx91-var-dart.dtsi"
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/ {
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model = "Variscite DART-MX91 on Sonata-Board";
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compatible = "variscite,var-dart-mx91-sonata",
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"variscite,var-dart-mx91",
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"fsl,imx91";
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aliases {
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ethernet0 = &eqos;
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ethernet1 = &fec;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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i2c0 = &lpi2c1;
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i2c1 = &lpi2c2;
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i2c2 = &lpi2c3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &lpuart1;
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serial1 = &lpuart2;
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serial2 = &lpuart3;
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serial3 = &lpuart4;
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serial4 = &lpuart5;
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serial5 = &lpuart6;
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};
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chosen {
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stdout-path = &lpuart1;
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};
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gpio-keys {
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compatible = "gpio-keys";
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button-home {
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label = "Home";
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linux,code = <KEY_HOME>;
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gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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button-up {
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label = "Up";
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linux,code = <KEY_UP>;
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gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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button-down {
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label = "Down";
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linux,code = <KEY_DOWN>;
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gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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button-back {
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label = "Back";
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linux,code = <KEY_BACK>;
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gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led-emmc {
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label = "eMMC";
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gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc0";
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};
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};
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reg_vref_1v8: regulator-adc-vref {
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compatible = "regulator-fixed";
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regulator-name = "vref_1v8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_rgb_sel: regulator-rgb-enable {
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compatible = "regulator-fixed";
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regulator-name = "RGBSEL";
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gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VDD_SD2_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <20000>;
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};
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reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x80000000 0 0x40000000>;
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reusable;
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size = <0 0x10000000>;
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linux,cma-default;
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};
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};
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};
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&adc1 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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/* Use external instead of internal RTC */
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&bbnsm_rtc {
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status = "disabled";
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};
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&eqos {
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mdio {
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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};
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};
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};
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};
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&fec {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_fec>;
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pinctrl-1 = <&pinctrl_fec_sleep>;
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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phy-handle = <ðphy1>;
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status = "okay";
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&lpi2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
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pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
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scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pca6408_1: gpio@20 {
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compatible = "nxp,pcal6408";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio1>;
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interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
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vcc-supply = <®_rgb_sel>;
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};
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pca6408_2: gpio@21 {
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compatible = "nxp,pcal6408";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio1>;
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interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
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vcc-supply = <®_rgb_sel>;
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};
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pca9534: gpio@22 {
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compatible = "nxp,pca9534";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio1>;
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interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
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};
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st33ktpm2xi2c: tpm@2e {
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compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
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reg = <0x2e>;
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};
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/* Capacitive touch controller */
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ft5x06_ts: touchscreen@38 {
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compatible = "edt,edt-ft5206";
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reg = <0x38>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_captouch>;
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reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio3>;
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interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
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touchscreen-size-x = <800>;
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touchscreen-size-y = <480>;
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touchscreen-inverted-x;
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touchscreen-inverted-y;
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wakeup-source;
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};
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/* USB Type-C Controller */
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typec@3d {
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compatible = "nxp,ptn5150";
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reg = <0x3d>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_extcon>;
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interrupt-parent = <&gpio4>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
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port {
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typec1_dr_sw: endpoint {
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remote-endpoint = <&usb1_drd_sw>;
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};
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};
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};
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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};
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};
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/* Console (J10) */
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* Header (J12.4, J12.6) */
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&lpuart6 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart6>;
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status = "okay";
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};
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&usbotg1 {
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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usb-role-switch;
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disable-over-current;
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samsung,picophy-pre-emp-curr-control = <3>;
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samsung,picophy-dc-vol-level-adjust = <7>;
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status = "okay";
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port {
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usb1_drd_sw: endpoint {
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remote-endpoint = <&typec1_dr_sw>;
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};
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};
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};
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&usbotg2 {
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disable-over-current;
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dr_mode = "host";
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status = "okay";
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};
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/* SD */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
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cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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no-sdio;
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no-mmc;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* GPIO Expanders shared IRQ */
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MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
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>;
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};
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pinctrl_captouch: captouchgrp {
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fsl,pins = <
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MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
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>;
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};
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pinctrl_extcon: extcongrp {
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fsl,pins = <
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MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x31e
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
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MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
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MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
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MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x37e
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MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
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MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
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MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
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MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
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MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
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MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
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MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
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MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
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>;
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};
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pinctrl_fec_sleep: fecsleepgrp {
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fsl,pins = <
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MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
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MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
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MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
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MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e
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MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
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MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
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MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
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MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
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MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
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MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
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MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
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MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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MX91_PAD_PDM_CLK__CAN1_TX 0x139e
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MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
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MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
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>;
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};
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pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp {
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fsl,pins = <
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MX91_PAD_I2C1_SCL__GPIO1_IO0 0x31e
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MX91_PAD_I2C1_SDA__GPIO1_IO1 0x31e
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x31e
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
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MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
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>;
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};
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pinctrl_uart6: uart6grp {
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fsl,pins = <
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MX91_PAD_GPIO_IO05__LPUART6_RX 0x31e
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MX91_PAD_GPIO_IO04__LPUART6_TX 0x31e
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
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MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
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MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
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MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
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MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
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MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
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MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
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MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
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MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
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MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
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MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
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MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
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MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
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MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
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MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
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MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
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MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
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MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
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MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
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>;
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};
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pinctrl_usdhc2_sleep: usdhc2sleepgrp {
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fsl,pins = <
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MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
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MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
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MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
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MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
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MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
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MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
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MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
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>;
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};
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pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
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fsl,pins = <
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MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
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>;
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};
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};
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