221 lines
5.5 KiB
Devicetree
221 lines
5.5 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright 2022,2026 NXP
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx93.dtsi"
|
|
#include "imx93-11x11-evk-common.dtsi"
|
|
|
|
/ {
|
|
model = "NXP i.MX93 11X11 EVK board";
|
|
compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
|
|
|
|
aliases {
|
|
mmc2 = &usdhc3;
|
|
};
|
|
|
|
reg_m2_pwr: regulator-m2-pwr {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "M.2-power";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
reg_usdhc3_vmmc: regulator-usdhc3 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "WLAN_EN";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
vin-supply = <®_m2_pwr>;
|
|
gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
|
|
/*
|
|
* IW612 wifi chip needs more delay than other wifi chips to complete
|
|
* the host interface initialization after power up, otherwise the
|
|
* internal state of IW612 may be unstable, resulting in the failure of
|
|
* the SDIO3.0 switch voltage.
|
|
*/
|
|
startup-delay-us = <20000>;
|
|
enable-active-high;
|
|
};
|
|
|
|
usdhc3_pwrseq: usdhc3_pwrseq {
|
|
compatible = "mmc-pwrseq-simple";
|
|
reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
bt_sco_codec: bt-sco-codec {
|
|
compatible = "linux,bt-sco";
|
|
#sound-dai-cells = <1>;
|
|
};
|
|
|
|
sound-bt-sco {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "bt-sco-audio";
|
|
simple-audio-card,format = "dsp_a";
|
|
simple-audio-card,bitclock-inversion;
|
|
simple-audio-card,frame-master = <&btcpu>;
|
|
simple-audio-card,bitclock-master = <&btcpu>;
|
|
|
|
btcpu: simple-audio-card,cpu {
|
|
sound-dai = <&sai1>;
|
|
dai-tdm-slot-num = <2>;
|
|
dai-tdm-slot-width = <16>;
|
|
};
|
|
|
|
simple-audio-card,codec {
|
|
sound-dai = <&bt_sco_codec 1>;
|
|
};
|
|
};
|
|
|
|
sound-micfil {
|
|
compatible = "fsl,imx-audio-card";
|
|
model = "micfil-audio";
|
|
|
|
pri-dai-link {
|
|
link-name = "micfil hifi";
|
|
format = "i2s";
|
|
|
|
cpu {
|
|
sound-dai = <&micfil>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&micfil {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pinctrl_pdm>;
|
|
pinctrl-1 = <&pinctrl_pdm_sleep>;
|
|
assigned-clocks = <&clk IMX93_CLK_PDM>;
|
|
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
|
|
assigned-clock-rates = <49152000>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pcal6524 {
|
|
m2-pcm-level-shifter-hog {
|
|
gpio-hog;
|
|
gpios = <19 GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
};
|
|
};
|
|
|
|
&sai1 {
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pinctrl_sai1>;
|
|
pinctrl-1 = <&pinctrl_sai1_sleep>;
|
|
assigned-clocks = <&clk IMX93_CLK_SAI1>;
|
|
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
|
|
assigned-clock-rates = <12288000>;
|
|
fsl,sai-mclk-direction-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
|
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
|
|
pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
|
|
mmc-pwrseq = <&usdhc3_pwrseq>;
|
|
vmmc-supply = <®_usdhc3_vmmc>;
|
|
bus-width = <4>;
|
|
keep-power-in-suspend;
|
|
non-removable;
|
|
wakeup-source;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_pdm: pdmgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_PDM_CLK__PDM_CLK 0x31e
|
|
MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e
|
|
MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_pdm_sleep: pdmsleepgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_PDM_CLK__GPIO1_IO08 0x31e
|
|
MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x31e
|
|
MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai1: sai1grp {
|
|
fsl,pins = <
|
|
MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
|
|
MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
|
|
MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
|
|
MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_sai1_sleep: sai1sleepgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SAI1_TXC__GPIO1_IO12 0x51e
|
|
MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x51e
|
|
MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x51e
|
|
MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x51e
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582
|
|
MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382
|
|
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382
|
|
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382
|
|
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382
|
|
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e
|
|
MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e
|
|
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e
|
|
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e
|
|
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e
|
|
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe
|
|
MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe
|
|
MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe
|
|
MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe
|
|
MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe
|
|
MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_sleep: usdhc3grpsleepgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD3_CLK__GPIO3_IO20 0x31e
|
|
MX93_PAD_SD3_CMD__GPIO3_IO21 0x31e
|
|
MX93_PAD_SD3_DATA0__GPIO3_IO22 0x31e
|
|
MX93_PAD_SD3_DATA1__GPIO3_IO23 0x31e
|
|
MX93_PAD_SD3_DATA2__GPIO3_IO24 0x31e
|
|
MX93_PAD_SD3_DATA3__GPIO3_IO25 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_wlan: usdhc3wlangrp {
|
|
fsl,pins = <
|
|
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
|
|
>;
|
|
};
|
|
};
|