1161 lines
30 KiB
Devicetree
1161 lines
30 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) Toradex
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*
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* https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95
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*/
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#include <dt-bindings/net/ti-dp83867.h>
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#include "imx95.dtsi"
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/ {
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aliases {
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can0 = &flexcan1;
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can1 = &flexcan2;
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can2 = &flexcan3;
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can3 = &flexcan4;
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eeprom0 = &som_eeprom;
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ethernet0 = &enetc_port0;
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i2c0 = &lpi2c3;
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i2c1 = &lpi2c2;
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i2c2 = &i3c2;
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i2c3 = &lpi2c8;
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i2c4 = &lpi2c4;
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i2c6 = &lpi2c5;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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rtc0 = &rtc_i2c;
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rtc1 = &scmi_bbm;
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serial0 = &lpuart3;
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serial1 = &lpuart7;
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serial2 = &lpuart1;
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serial3 = &lpuart2;
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usb0 = &usb3;
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usb1 = &usb2;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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};
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aquila_key_wake: gpio-key-wakeup {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
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status = "disabled";
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key-wakeup {
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/* Aquila CTRL_WAKE1_MICO# */
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gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
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label = "Wake Up";
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wakeup-source;
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linux,code = <KEY_WAKEUP>;
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};
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};
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clk_dsi2dp_refclk: clock-dsi2dp-refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en {
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compatible = "gpio-gate-clock";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>;
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clocks = <&clk_dsi2dp_refclk>;
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#clock-cells = <0>;
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/* CTRL_DP_CLK_EN */
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enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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};
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clk_serdes_eth_ref: clock-serdes-eth-ref {
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compatible = "gpio-gate-clock";
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#clock-cells = <0>;
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/* CTRL_ETH_REF_CLK_STBY */
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enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>;
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};
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reg_1p8v: regulator-1p8v {
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compatible = "regulator-fixed";
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regulator-max-microvolt = <1800000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "On-module +V1.8";
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};
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reg_dp_1p2v: regulator-dp-1p2v {
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compatible = "regulator-fixed";
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/* CTRL_DP_BRIDGE_EN */
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gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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regulator-max-microvolt = <1200000>;
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regulator-min-microvolt = <1200000>;
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regulator-name = "On-module +V1.2_DP";
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vin-supply = <®_1p8v>;
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};
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reg_usb1_vbus: regulator-usb1-vbus {
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compatible = "regulator-fixed";
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/* Aquila USB_1_EN */
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gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-name = "USB_1_EN";
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};
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reg_usb2_vbus: regulator-usb2-vbus {
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compatible = "regulator-fixed";
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/* Aquila USB_2_EN */
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gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-name = "USB_2_H_EN";
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};
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reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sd1_pwr_en>;
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/* Aquila SD_1_PWR_EN */
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gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <100000>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <3300000>;
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regulator-name = "SD_1_PWR_EN";
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startup-delay-us = <20000>;
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};
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reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
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compatible = "regulator-gpio";
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/* PMIC_SD_1_VSEL */
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gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "PMIC_SD_1_VSEL";
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states = <1800000 0x1>,
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<3300000 0x0>;
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};
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remoteproc-cm7 {
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compatible = "fsl,imx95-cm7";
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mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>;
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mbox-names = "tx", "rx", "rxdb";
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memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
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<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux_cma: linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x3c000000>;
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alloc-ranges = <0 0x80000000 0 0x7f000000>;
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linux,cma-default;
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};
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m7_reserved: memory@80000000 {
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reg = <0 0x80000000 0 0x1000000>;
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no-map;
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};
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rsc_table: rsc-table@88220000 {
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reg = <0 0x88220000 0 0x1000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@88000000 {
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reg = <0 0x88000000 0 0x8000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@88008000 {
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reg = <0 0x88008000 0 0x8000>;
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no-map;
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};
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vdev1vring0: vdev1vring0@88010000 {
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reg = <0 0x88010000 0 0x8000>;
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no-map;
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};
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vdev1vring1: vdev1vring1@88018000 {
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reg = <0 0x88018000 0 0x8000>;
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no-map;
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};
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vdevbuffer: vdevbuffer@88020000 {
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compatible = "shared-dma-pool";
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reg = <0 0x88020000 0 0x100000>;
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no-map;
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};
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};
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};
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/* Aquila ADC_[1-4] */
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&adc1 {
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vref-supply = <®_1p8v>;
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};
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/* Aquila ETH_1 */
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&enetc_port0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enetc0>;
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phy-handle = <ðphy1>;
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phy-mode = "rgmii-id";
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};
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/* Aquila CAN_1 */
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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};
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/* Aquila CAN_2 */
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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};
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/* Aquila CAN_3 */
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&flexcan3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan3>;
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};
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/* Aquila CAN_4 */
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&flexcan4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan4>;
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};
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/* Aquila QSPI_1 */
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&flexspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi1_8bit>,
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<&pinctrl_qspi_cs1>;
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};
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&gpio1 {
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gpio-line-names = "", /* 0 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"AQUILA_C24", /* 10 */
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"",
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"AQUILA_B17",
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"CTRL_GPIO_EXP_INT#",
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"AQUILA_B18";
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status = "okay";
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};
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&gpio2 {
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gpio-line-names = "", /* 0 */
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"",
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"",
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"",
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"",
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"",
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"",
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"AQUILA_B42",
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"",
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"AQUILA_B43";
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};
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&gpio3 {
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gpio-line-names = "", /* 0 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"", /* 10 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"AQUILA_A11",
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"", /* 20 */
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"AQUILA_B57",
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"AQUILA_B19";
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};
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&gpio4 {
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gpio-line-names = "", /* 0 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"", /* 10 */
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"",
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"",
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"",
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"",
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"",
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"",
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"AQUILA_C22",
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"AQUILA_C21",
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"AQUILA_C20",
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"", /* 20 */
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"",
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"",
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"AQUILA_C23",
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"AQUILA_D23",
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"AQUILA_D24",
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"",
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"AQUILA_D25";
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};
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&gpio5 {
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gpio-line-names = "", /* 0 */
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"",
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"", /* 10 */
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"",
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"",
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"AQUILA_B44",
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"AQUILA_B45";
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};
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/* Aquila I2C_2 */
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&i3c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i3c2>;
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i2c-scl-hz = <100000>;
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};
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/* Aquila I2C_1 */
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&lpi2c2 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c2>;
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pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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/* On-module I2C - I2C_SOM */
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&lpi2c3 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>;
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pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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som_gpio_expander_0: gpio@20 {
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compatible = "nxp,pcal6408";
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reg = <0x20>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-line-names =
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"AQUILA_C38", /* 0 */
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"PCIE_2_RESET#",
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"AQUILA_B77",
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"USB_2_H_EN",
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"BT_DISABLE#",
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"WIFI_DISABLE#",
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"CTRL_ETH_REF_CLK_STBY",
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"CTRL_DP_BRIDGE_EN";
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};
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som_gpio_expander_1: gpio@21 {
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compatible = "nxp,pcal6416";
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reg = <0x21>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio1>;
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interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-line-names =
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"AQUILA_C1", /* 0 */
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"AQUILA_C2",
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"AQUILA_C3",
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"AQUILA_C4",
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"AQUILA_C36",
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"AQUILA_B74",
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"AQUILA_B75",
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"USB_2_H_OC#",
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"AQUILA_B81",
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"PMIC_SD_1_VSEL",
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"ETH_1_INT#", /* 10 */
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"CTRL_TPM_INT#",
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"SPI_2_CS2_TPM",
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"PCIE_WAKE_WIFI#",
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"WIFI_WAKE_BT",
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"WIFI_WAKEUP_HOST";
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};
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som_dsi2dp_bridge: bridge@2c {
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compatible = "ti,sn65dsi86";
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reg = <0x2c>;
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clocks = <&clk_dsi2dp_refclk_en>;
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clock-names = "refclk";
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vcc-supply = <®_dp_1p2v>;
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vcca-supply = <®_dp_1p2v>;
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vccio-supply = <®_1p8v>;
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vpll-supply = <®_1p8v>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi2dp_in: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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dsi2dp_out: endpoint {
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data-lanes = <3 2 1 0>;
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};
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};
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};
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};
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rtc_i2c: rtc@32 {
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compatible = "epson,rx8130";
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reg = <0x32>;
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};
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temperature-sensor@48 {
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compatible = "ti,tmp1075";
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reg = <0x48>;
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};
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som_eeprom: eeprom@50 {
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compatible = "st,24c02", "atmel,24c02";
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reg = <0x50>;
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pagesize = <16>;
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};
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};
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/* Aquila I2C_4_CSI1 */
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&lpi2c4 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c4>;
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pinctrl-1 = <&pinctrl_lpi2c4_gpio>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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/* Aquila I2C_6 */
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&lpi2c5 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c5>;
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pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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/* Aquila I2C_3_DSI1/I2C_5_CSI2 */
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&lpi2c8 {
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c8>;
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pinctrl-1 = <&pinctrl_lpi2c8_gpio>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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};
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/* Aquila SPI_2 */
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&lpspi4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi4>;
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cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>,
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<&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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som_tpm: tpm@1 {
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compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
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reg = <0x1>;
|
|
interrupt-parent = <&som_gpio_expander_1>;
|
|
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
|
|
/*
|
|
* Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz
|
|
* here as lpspi4's per-clock (2x the max speed) is 24 MHz.
|
|
*/
|
|
spi-max-frequency = <12000000>;
|
|
};
|
|
};
|
|
|
|
/* Aquila SPI_1 */
|
|
&lpspi6 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_lpspi6>;
|
|
cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
/* Aquila UART_3, used as the Linux Console */
|
|
&lpuart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
};
|
|
|
|
/* Aquila UART_4 */
|
|
&lpuart2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
};
|
|
|
|
/* Aquila UART_1 */
|
|
&lpuart3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart3>;
|
|
uart-has-rtscts;
|
|
};
|
|
|
|
/* Aquila UART_2 */
|
|
&lpuart7 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart7>;
|
|
uart-has-rtscts;
|
|
};
|
|
|
|
&mu7 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */
|
|
&netc_emdio {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_emdio>;
|
|
|
|
status = "okay";
|
|
|
|
ethphy1: ethernet-phy@1 {
|
|
reg = <1>;
|
|
interrupt-parent = <&som_gpio_expander_1>;
|
|
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
|
|
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
|
};
|
|
};
|
|
|
|
&netcmix_blk_ctrl {
|
|
status = "okay";
|
|
};
|
|
|
|
&netc_blk_ctrl {
|
|
status = "okay";
|
|
};
|
|
|
|
&netc_timer {
|
|
status = "okay";
|
|
};
|
|
|
|
/* Aquila PCIE_1 */
|
|
&pcie0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie0>;
|
|
reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
/* On-module Wi-Fi or Aquila PCIE_2 */
|
|
&pcie1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie1>;
|
|
reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
/* Aquila I2S_1 */
|
|
&sai2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sai2>;
|
|
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
|
|
<&scmi_clk IMX95_CLK_SAI2>;
|
|
assigned-clock-parents = <0>, <0>, <0>, <0>,
|
|
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
|
|
assigned-clock-rates = <3932160000>,
|
|
<3612672000>, <393216000>,
|
|
<361267200>, <12288000>;
|
|
#sound-dai-cells = <0>;
|
|
fsl,sai-mclk-direction-output;
|
|
};
|
|
|
|
&scmi_bbm {
|
|
linux,code = <KEY_POWER>;
|
|
};
|
|
|
|
&thermal_zones {
|
|
/* PF09 Main PMIC */
|
|
pf09-thermal {
|
|
polling-delay = <2000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&scmi_sensor 2>;
|
|
|
|
trips {
|
|
trip0 {
|
|
hysteresis = <2000>;
|
|
temperature = <155000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
/* PF53 VDD_ARM PMIC */
|
|
pf53-arm-thermal {
|
|
polling-delay = <2000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&scmi_sensor 4>;
|
|
|
|
trips {
|
|
trip0 {
|
|
hysteresis = <2000>;
|
|
temperature = <155000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
/* PF53 VDD_SOC PMIC */
|
|
pf53-soc-thermal {
|
|
polling-delay = <2000>;
|
|
polling-delay-passive = <250>;
|
|
thermal-sensors = <&scmi_sensor 3>;
|
|
|
|
trips {
|
|
trip0 {
|
|
hysteresis = <2000>;
|
|
temperature = <155000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Aquila PWM_1 */
|
|
&tpm3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
|
};
|
|
|
|
/* Aquila PWM_2 */
|
|
&tpm6 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm2>;
|
|
};
|
|
|
|
/* Aquila PWM_3_DSI and PWM_4_DP */
|
|
&tpm5 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>;
|
|
};
|
|
|
|
/* Aquila USB_2, optional Bluetooth USB */
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
vbus-supply = <®_usb2_vbus>;
|
|
};
|
|
|
|
/* Aquila USB_1 */
|
|
&usb3 {
|
|
fsl,disable-port-power-control;
|
|
};
|
|
|
|
&usb3_dwc3 {
|
|
dr_mode = "otg";
|
|
adp-disable;
|
|
hnp-disable;
|
|
srp-disable;
|
|
usb-role-switch;
|
|
};
|
|
|
|
&usb3_phy {
|
|
vbus-supply = <®_usb1_vbus>;
|
|
};
|
|
|
|
/* On-module eMMC */
|
|
&usdhc1 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc1>;
|
|
pinctrl-1 = <&pinctrl_usdhc1>;
|
|
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
no-sdio;
|
|
no-sd;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
/* Aquila SD_1 */
|
|
&usdhc2 {
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>;
|
|
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>;
|
|
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
|
vqmmc-supply = <®_usdhc2_vqmmc>;
|
|
};
|
|
|
|
&wdog3 {
|
|
fsl,ext-reset-output;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
&scmi_iomuxc {
|
|
/* Aquila CTRL_WAKE1_MICO# */
|
|
pinctrl_ctrl_wake1_mico: ctrlwake1micogrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e>; /* Aquila D6 */
|
|
};
|
|
|
|
pinctrl_ctrl_dp_clk_en: dpclkengrp {
|
|
fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x11e>; /* CTRL_DP_CLK_EN */
|
|
};
|
|
|
|
/* Aquila ETH_2_XGMII_MDIO */
|
|
pinctrl_emdio: emdiogrp {
|
|
fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e>, /* Aquila B90 */
|
|
<IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e>; /* Aquila B89 */
|
|
};
|
|
|
|
/* Aquila ETH_1 */
|
|
pinctrl_enetc0: enetc0grp {
|
|
fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */
|
|
<IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */
|
|
<IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */
|
|
<IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */
|
|
<IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */
|
|
<IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */
|
|
<IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */
|
|
<IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */
|
|
<IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */
|
|
<IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */
|
|
<IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */
|
|
<IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */
|
|
};
|
|
|
|
/* Aquila CAN_1 */
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* Aquila B48 */
|
|
<IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* Aquila B49 */
|
|
};
|
|
|
|
/* Aquila CAN_2 */
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* Aquila B50 */
|
|
<IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* Aquila B51 */
|
|
};
|
|
|
|
/* Aquila CAN_3 */
|
|
pinctrl_flexcan3: flexcan3grp {
|
|
fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e>, /* Aquila B53 */
|
|
<IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e>; /* Aquila B54 */
|
|
};
|
|
|
|
/* Aquila CAN_4 */
|
|
pinctrl_flexcan4: flexcan4grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO04__CAN4_TX 0x39e>, /* Aquila B55 */
|
|
<IMX95_PAD_GPIO_IO05__CAN4_RX 0x39e>; /* Aquila B56 */
|
|
};
|
|
|
|
/* Aquila QSPI_1 (4 bit) */
|
|
pinctrl_flexspi1_4bit: flexspi14bitgrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */
|
|
<IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */
|
|
<IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */
|
|
<IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */
|
|
<IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */
|
|
<IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */
|
|
};
|
|
|
|
/* Aquila QSPI_1 (8 bit) */
|
|
pinctrl_flexspi1_8bit: flexspi18bitgrp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */
|
|
<IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */
|
|
<IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */
|
|
<IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */
|
|
<IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */
|
|
<IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe>, /* Aquila B70 */
|
|
<IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe>, /* Aquila B71 */
|
|
<IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe>, /* Aquila B72 */
|
|
<IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe>, /* Aquila B73 */
|
|
<IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */
|
|
};
|
|
|
|
/* Aquila GPIO_01 */
|
|
pinctrl_gpio_1: gpio1grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x31e>; /* Aquila D23 */
|
|
};
|
|
|
|
/* Aquila GPIO_02 */
|
|
pinctrl_gpio_2: gpio2grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x31e>; /* Aquila D24 */
|
|
};
|
|
|
|
/* Aquila GPIO_03 */
|
|
pinctrl_gpio_3: gpio3grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x31e>; /* Aquila D25 */
|
|
};
|
|
|
|
/* Aquila GPIO_04 */
|
|
pinctrl_gpio_4: gpio4grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x31e>; /* Aquila C20 */
|
|
};
|
|
|
|
/* Aquila GPIO_05 */
|
|
pinctrl_gpio_5: gpio5grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x31e>; /* Aquila C21 */
|
|
};
|
|
|
|
/* Aquila GPIO_06 */
|
|
pinctrl_gpio_6: gpio6grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x31e>; /* Aquila C22 */
|
|
};
|
|
|
|
/* Aquila GPIO_07 */
|
|
pinctrl_gpio_7: gpio7grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x31e>; /* Aquila C23 */
|
|
};
|
|
|
|
/* Aquila GPIO_08 */
|
|
pinctrl_gpio_8: gpio8grp {
|
|
fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* Aquila C24 */
|
|
};
|
|
|
|
/* Aquila GPIO_09_CSI_1 */
|
|
pinctrl_gpio_9_csi_1: gpio9csi1grp {
|
|
fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* Aquila B17 */
|
|
};
|
|
|
|
/* Aquila GPIO_10_CSI_1 */
|
|
pinctrl_gpio_10_csi_1: gpio10csi1grp {
|
|
fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* Aquila B18 */
|
|
};
|
|
|
|
/* Aquila GPIO_11_CSI_1 */
|
|
pinctrl_gpio_11_csi_1: gpio11csi1grp {
|
|
fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x31e>; /* Aquila A11*/
|
|
};
|
|
|
|
/* Aquila GPIO_12_CSI_1 */
|
|
pinctrl_gpio_12_csi_1: gpio12csi1grp {
|
|
fsl,pins = <IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x31e>; /* Aquila B19 */
|
|
};
|
|
|
|
/* Aquila GPIO_17_DSI_1 */
|
|
pinctrl_gpio_17_dsi_1: gpio17dsi1grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x31e>; /* Aquila B42 */
|
|
};
|
|
|
|
/* Aquila GPIO_18_DSI_1 */
|
|
pinctrl_gpio_18_dsi_1: gpio18dsi1grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x31e>; /* Aquila B43 */
|
|
};
|
|
|
|
/* Aquila GPIO_19_DSI_1 */
|
|
pinctrl_gpio_19_dsi_1: gpio19dsi1grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e>; /* Aquila B44 */
|
|
};
|
|
|
|
/* Aquila GPIO_20_DSI_1 */
|
|
pinctrl_gpio_20_dsi_1: gpio20dsi1grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e>; /* Aquila B45 */
|
|
};
|
|
|
|
/* Aquila GPIO_21_DP */
|
|
pinctrl_gpio_21_dp: gpio21dpgrp {
|
|
fsl,pins = <IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x31e>; /* Aquila B57 */
|
|
};
|
|
|
|
pinctrl_ctrl_gpio_exp_int: gpioexpintgrp {
|
|
fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* CTRL_GPIO_EXP_INT# */
|
|
};
|
|
|
|
/* Aquila I2C_2 */
|
|
pinctrl_i3c2: i3c2cgrp {
|
|
fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* Aquila C17 */
|
|
<IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* Aquila C16 */
|
|
};
|
|
|
|
/* Aquila I2C_1 as GPIOs */
|
|
pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
|
|
fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* Aquila D8 */
|
|
<IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* Aquila D7 */
|
|
};
|
|
|
|
/* Aquila I2C_1 */
|
|
pinctrl_lpi2c2: lpi2c2grp {
|
|
fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* Aquila D8 */
|
|
<IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* Aquila D7 */
|
|
};
|
|
|
|
/* On-module I2C as GPIOs */
|
|
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* I2C_SOM_SDA */
|
|
<IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* I2C_SOM_SCL */
|
|
};
|
|
|
|
/* On-module I2C */
|
|
pinctrl_lpi2c3: lpi2c3grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* I2C_SOM_SDA */
|
|
<IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* I2C_SOM_SCL */
|
|
};
|
|
|
|
/* Aquila I2C_4_CSI1 as GPIO */
|
|
pinctrl_lpi2c4_gpio: lpi2c4gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>, /* Aquila A12 */
|
|
<IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>; /* Aquila A13 */
|
|
};
|
|
|
|
/* Aquila I2C_4_CSI1 */
|
|
pinctrl_lpi2c4: lpi2c4grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>, /* Aquila A12 */
|
|
<IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>; /* Aquila A13 */
|
|
};
|
|
|
|
/* Aquila I2C_6 as GPIO */
|
|
pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* Aquila C18 */
|
|
<IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* Aquila C19 */
|
|
};
|
|
|
|
/* Aquila I2C_6 */
|
|
pinctrl_lpi2c5: lpi2c5grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* Aquila C18 */
|
|
<IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* Aquila C19 */
|
|
};
|
|
|
|
/* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */
|
|
pinctrl_lpi2c8_gpio: lpi2c8gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x40001b9e>, /* Aquila C5/B40 */
|
|
<IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x40001b9e>; /* Aquila C6/B41 */
|
|
};
|
|
|
|
/* Aquila I2C_3_DSI1/I2C_5_CSI2 */
|
|
pinctrl_lpi2c8: lpi2c8grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x40001b9e>, /* Aquila C5/B40 */
|
|
<IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x40001b9e>; /* Aquila C6/B41 */
|
|
};
|
|
|
|
/* Aquila SPI_2 */
|
|
pinctrl_lpspi4: lpspi4grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* Aquila D16 */
|
|
<IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* Aquila D15 */
|
|
<IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x3fe>, /* Aquila D17 */
|
|
<IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x3fe>; /* Aquila D14 */
|
|
};
|
|
|
|
/* Aquila SPI_1 */
|
|
pinctrl_lpspi6: lpspi6grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* Aquila D9 */
|
|
<IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* Aquila D10 */
|
|
<IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* Aquila D11 */
|
|
<IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* Aquila D12 */
|
|
};
|
|
|
|
/* Aquila PCIE_1 */
|
|
pinctrl_pcie0: pcie0grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* Aquila C37 */
|
|
};
|
|
|
|
/* Aquila PCIE_2 */
|
|
pinctrl_pcie1: pcie1grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* Aquila C34 */
|
|
};
|
|
|
|
/* Aquila QSPI_1_CS1# */
|
|
pinctrl_qspi_cs1: qspics1grp {
|
|
fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>; /* Aquila B66 */
|
|
};
|
|
|
|
/* Aquila QSPI_1_CS2# as GPIO */
|
|
pinctrl_qspi_cs2_gpio: qspics2gpiogrp {
|
|
fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x3fe>; /* Aquila B62 */
|
|
};
|
|
|
|
/* Aquila I2S_1 */
|
|
pinctrl_sai2: sai2grp {
|
|
fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x11e>, /* Aquila B21 */
|
|
<IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x11e>, /* Aquila B20 */
|
|
<IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x11e>, /* Aquila B23 */
|
|
<IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x11e>; /* Aquila B22 */
|
|
};
|
|
|
|
pinctrl_sai2_mclk: sai2mclkgrp {
|
|
fsl,pins = <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e>; /* Aquila B24 */
|
|
};
|
|
|
|
/* Aquila SD_1_CD# as GPIO */
|
|
pinctrl_sd1_cd_gpio: sd1cdgpiogrp {
|
|
fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* Aquila A1 */
|
|
};
|
|
|
|
/* Aquila SD_1_PWR_EN */
|
|
pinctrl_sd1_pwr_en: sd1pwrengpiogrp {
|
|
fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* Aquila A6 */
|
|
};
|
|
|
|
/* Aquila PWM_1 */
|
|
pinctrl_pwm1: tpm3ch3grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x11e>; /* Aquila C25 */
|
|
};
|
|
|
|
/* Aquila PWM_3_DSI as GPIO */
|
|
pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x11e>; /* Aquila B46 */
|
|
};
|
|
|
|
/* Aquila PWM_3_DSI */
|
|
pinctrl_pwm3_dsi: tpm5ch0grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* Aquila B46 */
|
|
};
|
|
|
|
/* Aquila PWM_4_DP */
|
|
pinctrl_pwm4_dp: tpm5ch3grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO26__TPM5_CH3 0x11e>; /* Aquila B58 */
|
|
};
|
|
|
|
/* Aquila PWM_2 */
|
|
pinctrl_pwm2: tpm6ch0grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO08__TPM6_CH0 0x11e>; /* Aquila C26 */
|
|
};
|
|
|
|
/* Aquila UART_3 */
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* Aquila D20 */
|
|
<IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* Aquila D19 */
|
|
};
|
|
|
|
/* Aquila UART_4 */
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>, /* Aquila D22 */
|
|
<IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>; /* Aquila D21 */
|
|
};
|
|
|
|
/* Aquila UART_1 */
|
|
pinctrl_uart3: uart3grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* Aquila B37 */
|
|
<IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>, /* Aquila B35 */
|
|
<IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x31e>, /* Aquila B36 */
|
|
<IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x31e>; /* Aquila B38 */
|
|
};
|
|
|
|
/* Aquila UART_2 */
|
|
pinctrl_uart7: uart7grp {
|
|
fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e>, /* Aquila B33 */
|
|
<IMX95_PAD_GPIO_IO37__LPUART7_RX 0x31e>, /* Aquila B31 */
|
|
<IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* Aquila B32 */
|
|
<IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* Aquila B34 */
|
|
};
|
|
|
|
/* On-module eMMC */
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* eMMC_CLK */
|
|
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* eMMC_CMD */
|
|
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* eMMC_DATA0 */
|
|
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* eMMC_DATA1 */
|
|
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* eMMC_DATA2 */
|
|
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* eMMC_DATA3 */
|
|
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* eMMC_DATA4 */
|
|
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* eMMC_DATA5 */
|
|
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* eMMC_DATA6 */
|
|
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* eMMC_DATA7 */
|
|
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* eMMC_STROBE */
|
|
};
|
|
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
|
fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* eMMC_CLK */
|
|
<IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* eMMC_CMD */
|
|
<IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* eMMC_DATA0 */
|
|
<IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* eMMC_DATA1 */
|
|
<IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* eMMC_DATA2 */
|
|
<IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* eMMC_DATA3 */
|
|
<IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* eMMC_DATA4 */
|
|
<IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* eMMC_DATA5 */
|
|
<IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* eMMC_DATA6 */
|
|
<IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* eMMC_DATA7 */
|
|
<IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* eMMC_STROBE */
|
|
};
|
|
|
|
/* Aquila SD_1 */
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* Aquila A5 */
|
|
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* Aquila A7 */
|
|
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* Aquila A3 */
|
|
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* Aquila A2 */
|
|
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* Aquila A10 */
|
|
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* Aquila A8 */
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* Aquila A5 */
|
|
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* Aquila A7 */
|
|
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* Aquila A3 */
|
|
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* Aquila A2 */
|
|
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* Aquila A10 */
|
|
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* Aquila A8 */
|
|
};
|
|
|
|
pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
|
|
fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* Aquila A5 */
|
|
<IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* Aquila A7 */
|
|
<IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* Aquila A3 */
|
|
<IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* Aquila A2 */
|
|
<IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* Aquila A10 */
|
|
<IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* Aquila A8 */
|
|
};
|
|
};
|