623 lines
13 KiB
Devicetree
623 lines
13 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Variscite Sonata carrier board for DART-MX95
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*
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* Link: https://variscite.com/carrier-boards/sonata-board/
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*
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* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
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*
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*/
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#include "imx95-var-dart.dtsi"
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/ {
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model = "Variscite DART-MX95 on Sonata-Board";
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compatible = "variscite,var-dart-mx95-sonata",
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"variscite,var-dart-mx95",
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"fsl,imx95";
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aliases {
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ethernet0 = &enetc_port0;
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ethernet1 = &enetc_port1;
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ethernet2 = &enetc_port2;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &lpuart1;
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};
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chosen {
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stdout-path = &lpuart1;
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};
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clk_osc_can0: clock-osc-40m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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};
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typec_con: connector {
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compatible = "usb-c-connector";
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data-role = "dual";
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label = "USB-C";
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op-sink-microwatt = <0>;
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power-role = "dual";
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self-powered;
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sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
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source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
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try-power-role = "sink";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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typec_con_hs: endpoint {
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remote-endpoint = <&usb3_data_hs>;
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};
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};
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port@1 {
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reg = <1>;
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typec_con_ss: endpoint {
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remote-endpoint = <&usb3_data_ss>;
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};
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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button-back {
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gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
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label = "Back";
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wakeup-source;
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linux,code = <KEY_BACK>;
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};
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button-down {
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gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
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label = "Down";
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wakeup-source;
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linux,code = <KEY_DOWN>;
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};
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button-home {
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gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
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label = "Home";
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wakeup-source;
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linux,code = <KEY_HOME>;
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};
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button-up {
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gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
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label = "Up";
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wakeup-source;
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linux,code = <KEY_UP>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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led-heartbeat {
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label = "Heartbeat";
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gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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reg_phy1_supply: regulator-phy1 {
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compatible = "regulator-fixed";
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regulator-name = "SUPPLY_PHY1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&pca6408_2 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <10000>;
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regulator-always-on;
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};
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reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VDD_SD2_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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off-on-delay-us = <12000>;
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};
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sfp0: sfp {
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compatible = "sff,sfp";
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i2c-bus = <&lpi2c3>;
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los-gpios = <&pca9534 1 GPIO_ACTIVE_HIGH>;
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maximum-power-milliwatt = <2000>;
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};
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};
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&enetc_port1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enetc1>;
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phy-handle = <ðphy1>;
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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status = "okay";
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};
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&enetc_port2 {
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phy-mode = "10gbase-r";
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sfp = <&sfp0>;
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status = "okay";
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&lpi2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
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pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
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scl-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pca9534: gpio@22 {
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compatible = "nxp,pca9534";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio5>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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pcie2-sel-hog {
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gpio-hog;
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gpios = <6 GPIO_ACTIVE_HIGH>;
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output-low;
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line-name = "pcie-clk-sw";
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};
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sfp-sel-hog {
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gpio-hog;
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gpios = <5 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "sfp-sw";
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};
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};
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/* Capacitive touch controller */
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ft5x06_ts: touchscreen@38 {
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compatible = "edt,edt-ft5206";
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reg = <0x38>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_captouch>;
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reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio5>;
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interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
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touchscreen-size-x = <800>;
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touchscreen-size-y = <480>;
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touchscreen-inverted-x;
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touchscreen-inverted-y;
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wakeup-source;
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};
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typec@3d {
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compatible = "nxp,ptn5150";
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reg = <0x3d>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ptn5150>;
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interrupt-parent = <&gpio5>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
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port {
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typec_dr_sw: endpoint {
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remote-endpoint = <&usb3_drd_sw>;
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};
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};
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};
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/* DS1337 RTC module */
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rtc>;
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interrupt-parent = <&gpio5>;
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interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
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wakeup-source;
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};
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};
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&lpi2c4 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c4>;
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pinctrl-1 = <&pinctrl_lpi2c4>;
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status = "okay";
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};
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&lpi2c8 {
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pca6408_1: gpio@20 {
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compatible = "nxp,pcal6408";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio5>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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};
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pca6408_2: gpio@21 {
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compatible = "nxp,pcal6408";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&gpio5>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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};
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st33ktpm2xi2c: tpm@2e {
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compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
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reg = <0x2e>;
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label = "tpm";
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reset-gpios = <&pca9534 0 GPIO_ACTIVE_HIGH>;
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};
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};
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&lpspi7 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi7>;
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cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>,
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<&gpio1 7 GPIO_ACTIVE_LOW>;
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status = "okay";
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/* Resistive touch controller */
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ads7846: touchscreen@0 {
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compatible = "ti,ads7846";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_restouch>;
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interrupt-parent = <&gpio2>;
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interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
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pendown-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
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spi-max-frequency = <1500000>;
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wakeup-source;
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ti,x-min = /bits/ 16 <125>;
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ti,x-max = /bits/ 16 <4008>;
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ti,y-min = /bits/ 16 <282>;
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ti,y-max = /bits/ 16 <3864>;
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ti,x-plate-ohms = /bits/ 16 <180>;
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ti,pressure-max = /bits/ 16 <255>;
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ti,debounce-max = /bits/ 16 <10>;
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ti,debounce-tol = /bits/ 16 <3>;
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ti,debounce-rep = /bits/ 16 <1>;
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ti,settle-delay-usec = /bits/ 16 <150>;
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ti,keep-vref-on;
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};
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/* CAN controller */
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can0: can@1 {
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compatible = "microchip,mcp251xfd";
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reg = <1>;
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clocks = <&clk_osc_can0>;
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interrupt-parent = <&gpio5>;
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interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
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microchip,rx-int-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can>;
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spi-max-frequency = <12000000>;
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};
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};
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/* Console */
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* Header (J12.4, J12.6) */
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&lpuart8 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart8>;
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status = "okay";
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};
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&netc_emdio {
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <100000>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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};
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};
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};
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&pcie0 {
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reset-gpio = <&pca6408_2 3 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie1 {
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reset-gpio = <&pca6408_2 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&usb2 {
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dr_mode = "host";
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adp-disable;
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hnp-disable;
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srp-disable;
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disable-over-current;
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status = "okay";
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};
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&usb3 {
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status = "okay";
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};
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&usb3_dwc3 {
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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adp-disable;
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usb-role-switch;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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status = "okay";
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port {
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usb3_drd_sw: endpoint {
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remote-endpoint = <&typec_dr_sw>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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usb3_data_hs: endpoint {
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remote-endpoint = <&typec_con_hs>;
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};
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};
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port@1 {
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reg = <1>;
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usb3_data_ss: endpoint {
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remote-endpoint = <&typec_con_ss>;
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};
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};
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};
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};
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&usb3_phy {
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fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>;
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fsl,phy-pcs-tx-swing-full-percent = <100>;
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fsl,phy-tx-preemp-amp-tune-microamp = <600>;
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fsl,phy-tx-vboost-level-microvolt = <1156>;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&scmi_iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* GPIO Expanders shared IRQ */
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IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x31e
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>;
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};
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pinctrl_can: cangrp {
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fsl,pins = <
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IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x31e
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IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x31e
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>;
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};
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pinctrl_captouch: captouchgrp {
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fsl,pins = <
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IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e
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>;
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};
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pinctrl_enetc1: enetc1grp {
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fsl,pins = <
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IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x57e
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IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e
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IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e
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IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e
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IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e
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IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e
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IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x57e
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IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e
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IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e
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IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e
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IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e
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IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x37e
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>;
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};
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pinctrl_flexcan1: flexcan1grp {
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fsl,pins = <
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IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e
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IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e
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>;
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};
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pinctrl_gpio_leds: ledgrp {
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fsl,pins = <
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IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x31e
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>;
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};
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pinctrl_lpi2c3: lpi2c3grp {
|
|
fsl,pins = <
|
|
IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
|
|
IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
|
|
>;
|
|
};
|
|
|
|
pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
|
|
fsl,pins = <
|
|
IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x31e
|
|
IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_lpi2c4: lpi2c4grp {
|
|
fsl,pins = <
|
|
IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
|
|
IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
|
|
>;
|
|
};
|
|
|
|
pinctrl_lpspi7: lpspi7grp {
|
|
fsl,pins = <
|
|
/* j16.4 ADS7846 */
|
|
IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe
|
|
/* j14.4 MCP2518FDT */
|
|
IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x3fe
|
|
/* j25.2 spidev */
|
|
IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x3fe
|
|
IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe
|
|
IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe
|
|
IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe
|
|
>;
|
|
};
|
|
|
|
pinctrl_ptn5150: ptn5150grp {
|
|
fsl,pins = <
|
|
IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
|
fsl,pins = <
|
|
IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_restouch: restouchgrp {
|
|
fsl,pins = <
|
|
IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_rtc: rtcgrp {
|
|
fsl,pins = <
|
|
IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
|
|
IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart8: uart8grp {
|
|
fsl,pins = <
|
|
IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e
|
|
IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
|
fsl,pins = <
|
|
IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
|
|
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
|
|
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
|
|
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
|
|
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
|
|
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
|
|
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
|
|
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
|
|
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
|
|
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
|
|
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
|
|
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
|
|
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
|
|
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
|
|
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
|
|
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
|
|
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
|
|
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
|
|
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
|
>;
|
|
};
|
|
};
|