lastdragon/linux-kernel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
7.2.3
linux-kernel/linux-7.2.3/arch/arm64/boot/dts/freescale/imx952-evk.dts
T
lastdragon ad2088d178 Resguardo inicial
2026-09-06 12:53:21 -06:00

870 lines
22 KiB
Devicetree
Raw Permalink Blame History

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025-2026 NXP
*/
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "imx952.dtsi"
#define FALLING_EDGE BIT(0)
#define RISING_EDGE BIT(1)
#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */
#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */
#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */
#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */
#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */
/ {
model = "NXP i.MX952 EVK board";
compatible = "fsl,imx952-evk", "fsl,imx952";
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial4 = &lpuart5;
spi6 = &lpspi7;
};
bt_sco_codec: audio-codec-bt-sco {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
};
chosen {
stdout-path = &lpuart1;
};
dmic: dmic {
compatible = "dmic-codec";
#sound-dai-cells = <0>;
num-channels = <2>;
};
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
fan0: pwm-fan {
compatible = "pwm-fan";
#cooling-cells = <2>;
pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>;
cooling-levels = <64 128 192 255>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x7f000000>;
size = <0 0x3c000000>;
linux,cma-default;
reusable;
};
};
flexcan1_phy: can-phy0 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
max-bitrate = <8000000>;
enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>;
standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>;
};
flexcan2_phy: can-phy1 {
compatible = "nxp,tjr1443";
#phy-cells = <0>;
max-bitrate = <8000000>;
enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>;
standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SW";
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8_SW";
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-pwr";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&i2c4_pcal6408 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VDD_SD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <12000>;
};
reg_usb_vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "USB_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,bitclock-inversion;
simple-audio-card,bitclock-master = <&btcpu>;
simple-audio-card,format = "dsp_a";
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,codec {
sound-dai = <&bt_sco_codec 1>;
};
btcpu: simple-audio-card,cpu {
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
sound-dai = <&sai1>;
};
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
format = "i2s";
link-name = "micfil hifi";
codec {
sound-dai = <&dmic>;
};
cpu {
sound-dai = <&micfil>;
};
};
};
sound-wm8962 {
compatible = "fsl,imx-audio-wm8962";
audio-asrc = <&asrc1>;
audio-codec = <&wm8962>;
audio-cpu = <&sai3>;
audio-routing = "Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC",
"IN1R", "AMIC";
hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
model = "wm8962-audio";
pinctrl-0 = <&pinctrl_hp>;
pinctrl-names = "default";
};
};
&asrc1 {
assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>,
<&scmi_clk IMX952_CLK_AUDIOPLL2>,
<&scmi_clk IMX952_CLK_ASRC1>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>, <49152000>;
fsl,asrc-rate = <48000>;
status = "okay";
};
&asrc2 {
assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>,
<&scmi_clk IMX952_CLK_AUDIOPLL2>,
<&scmi_clk IMX952_CLK_ASRC2>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>, <49152000>;
fsl,asrc-rate = <48000>;
status = "okay";
};
/* pin conflict with PDM */
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
phys = <&flexcan1_phy>;
status = "disabled";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
phys = <&flexcan2_phy>;
status = "okay";
};
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
status = "okay";
adp5585: io-expander@34 {
compatible = "adi,adp5585-00", "adi,adp5585";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
gpio-reserved-ranges = <5 1>;
#pwm-cells = <3>;
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
i2c3_pcal6408: gpio@20 {
compatible = "nxp,pcal6408";
reg = <0x20>;
#gpio-cells = <2>;
gpio-controller;
vcc-supply = <&reg_3p3v>;
};
};
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c4>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&scmi_clk IMX952_CLK_SAI3>;
AVDD-supply = <&reg_audio_pwr>;
CPVDD-supply = <&reg_audio_pwr>;
DBVDD-supply = <&reg_audio_pwr>;
DCVDD-supply = <&reg_audio_pwr>;
gpio-cfg = < 0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
MICVDD-supply = <&reg_audio_pwr>;
PLLVDD-supply = <&reg_audio_pwr>;
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
};
i2c4_pcal6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_pcal6408>;
vcc-supply = <&reg_3p3v>;
};
};
&lpi2c6 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c6>;
status = "okay";
pcal6416: gpio@21 {
compatible = "nxp,pcal6416";
#gpio-cells = <2>;
gpio-controller;
reg = <0x21>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6416>;
vcc-supply = <&reg_3p3v>;
pdm-can-sel-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-low;
};
mqs-en-hog {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
output-low;
};
};
};
&lpi2c7 {
clock-frequency = <1000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c7>;
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6524>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio5>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio5>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5110>;
typec_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>;
op-sink-microwatt = <0>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
};
&lpuart1 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&lpuart5 {
/* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&lpspi7 {
cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi7>;
status = "okay";
};
&micfil {
assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>,
<&scmi_clk IMX952_CLK_AUDIOPLL2>,
<&scmi_clk IMX952_CLK_PDM>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>, <49152000>;
pinctrl-0 = <&pinctrl_pdm>;
pinctrl-1 = <&pinctrl_pdm_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
};
&sai1 {
assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>,
<&scmi_clk IMX952_CLK_AUDIOPLL2>,
<&scmi_clk IMX952_CLK_SAI1>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>, <12288000>;
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_sleep>;
pinctrl-names = "default", "sleep";
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai3 {
assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>,
<&scmi_clk IMX952_CLK_AUDIOPLL2>,
<&scmi_clk IMX952_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX952_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>, <3612672000>,
<393216000>, <361267200>, <12288000>;
pinctrl-0 = <&pinctrl_sai3>;
pinctrl-1 = <&pinctrl_sai3_sleep>;
pinctrl-names = "default", "sleep";
fsl,sai-amix-mode = "bypass";
fsl,sai-mclk-direction-output;
status = "okay";
};
&scmi_misc {
nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1
BRD_SM_CTRL_M2E_WAKE 1
BRD_SM_CTRL_BT_WAKE 1
BRD_SM_CTRL_M2M_WAKE 1
BRD_SM_CTRL_BUTTON 1>;
};
&tpm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm3>;
status = "okay";
};
&tpm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm6>;
status = "okay";
};
&usb1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usb2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_vbus>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&scmi_iomuxc {
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e
IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e
IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e
>;
};
pinctrl_hp: hpgrp {
fsl,pins = <
IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x31e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e
IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins = <
IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e
IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e
>;
};
pinctrl_i2c4_pcal6408: i2c4pcal6408grp {
fsl,pins = <
IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e
>;
};
pinctrl_lpi2c6: lpi2c6grp {
fsl,pins = <
IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e
IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e
IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e
>;
};
pinctrl_lpspi7: lpspi7grp {
fsl,pins = <
IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e
IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e
IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e
IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e
>;
};
pinctrl_pcal6416: pcal6416grp {
fsl,pins = <
IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e
IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x31e
>;
};
pinctrl_pdm_sleep: pdmsleepgrp {
fsl,pins = <
IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x31e
IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x31e
>;
};
pinctrl_ptn5110: ptn5110grp {
fsl,pins = <
IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x31e
IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e
IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e
IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x31e
>;
};
pinctrl_sai1_sleep: sai1sleepgrp {
fsl,pins = <
IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x51e
IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x51e
IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x51e
IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x51e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x31e
IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x31e
IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x31e
IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x31e
IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x31e
>;
};
pinctrl_sai3_sleep: sai3sleepgrp {
fsl,pins = <
IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x31e
IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x31e
IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x31e
IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x31e
IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x31e
>;
};
pinctrl_tpm3: tpm3grp {
fsl,pins = <
IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e
>;
};
pinctrl_tpm6: tpm6grp {
fsl,pins = <
IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e
IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e
IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e
IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e
IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e
IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e
IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e
IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e
IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e
IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e
IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e
IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e
IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e
IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e
IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e
IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e
IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e
IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e
IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e
IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e
IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e
IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e
IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e
IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e
IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e
IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e
IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e
IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e
IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e
IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e
IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e
IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e
IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e
IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e
IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e
IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e
IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e
IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e
IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e
IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e
IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e
>;
};
pinctrl_xspi1: xspi1grp {
fsl,pins = <
IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x39e
IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x39e
IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x39e
IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x39e
IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x39e
IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x39e
IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x39e
IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x39e
IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x39e
IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x39e
IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x39e
>;
};
pinctrl_xspi1_reset: xspi1-reset-grp {
fsl,pins = <
IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x39e
>;
};
};
&xspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_xspi1>;
status = "okay";
mt35xu01gbba: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_xspi1_reset>;
reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <200000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
Reference in New Issue View Git Blame Copy Permalink