291 lines
5.5 KiB
Plaintext
291 lines
5.5 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
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&{/} {
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vreg_0p9: regulator-0v9 {
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compatible = "regulator-fixed";
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regulator-name = "VREG_0P9";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vreg_1p8: regulator-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "VREG_1P8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&remoteproc_wpss {
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status = "disabled";
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};
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&spi11 {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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st33htpm0: tpm@0 {
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compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi";
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reg = <0>;
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spi-max-frequency = <20000000>;
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};
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};
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&pcie0 {
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perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
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pinctrl-names = "default";
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iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
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<0x100 &apps_smmu 0x1c01 0x1>,
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<0x208 &apps_smmu 0x1c04 0x1>,
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<0x210 &apps_smmu 0x1c05 0x1>,
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<0x218 &apps_smmu 0x1c06 0x1>,
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<0x300 &apps_smmu 0x1c07 0x1>,
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<0x400 &apps_smmu 0x1c08 0x1>,
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<0x500 &apps_smmu 0x1c09 0x1>,
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<0x501 &apps_smmu 0x1c10 0x1>;
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status = "okay";
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};
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&pcie0_phy {
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vdda-phy-supply = <&vreg_l10c_0p88>;
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vdda-pll-supply = <&vreg_l6b_1p2>;
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status = "okay";
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};
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&pcie0_port {
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#address-cells = <3>;
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#size-cells = <2>;
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pcie@0,0 {
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compatible = "pci1179,0623";
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reg = <0x10000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x2 0xff>;
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vddc-supply = <&vreg_0p9>;
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vdd18-supply = <&vreg_1p8>;
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vdd09-supply = <&vreg_0p9>;
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vddio1-supply = <&vreg_1p8>;
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vddio2-supply = <&vreg_1p8>;
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vddio18-supply = <&vreg_1p8>;
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i2c-parent = <&i2c1 0x33>;
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resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie0_tc9563_resx_n>;
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pinctrl-names = "default";
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pcie@1,0 {
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reg = <0x20800 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x3 0xff>;
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};
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pcie@2,0 {
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reg = <0x21000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x4 0xff>;
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};
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pcie@3,0 {
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reg = <0x21800 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x5 0xff>;
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pci@0,0 {
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reg = <0x50000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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pci@0,1 {
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reg = <0x50100 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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};
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};
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};
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&pcie1 {
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iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
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<0x100 &apps_smmu 0x1c81 0x1>,
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<0x208 &apps_smmu 0x1c84 0x1>,
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<0x210 &apps_smmu 0x1c85 0x1>,
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<0x218 &apps_smmu 0x1c86 0x1>,
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<0x300 &apps_smmu 0x1c87 0x1>,
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<0x408 &apps_smmu 0x1c90 0x1>,
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<0x410 &apps_smmu 0x1c91 0x1>,
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<0x418 &apps_smmu 0x1c92 0x1>,
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<0x500 &apps_smmu 0x1c93 0x1>,
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<0x600 &apps_smmu 0x1c94 0x1>,
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<0x700 &apps_smmu 0x1c95 0x1>,
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<0x701 &apps_smmu 0x1c96 0x1>,
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<0x800 &apps_smmu 0x1c97 0x1>,
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<0x900 &apps_smmu 0x1c98 0x1>,
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<0x901 &apps_smmu 0x1c99 0x1>;
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};
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&pcie1_switch0_dsp1 {
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#address-cells = <3>;
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#size-cells = <2>;
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pcie@0,0 {
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compatible = "pci1179,0623";
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reg = <0x30000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x2 0xff>;
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vddc-supply = <&vdd_ntn_0p9>;
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vdd18-supply = <&vdd_ntn_1p8>;
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vdd09-supply = <&vdd_ntn_0p9>;
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vddio1-supply = <&vdd_ntn_1p8>;
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vddio2-supply = <&vdd_ntn_1p8>;
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vddio18-supply = <&vdd_ntn_1p8>;
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i2c-parent = <&i2c1 0x77>;
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resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie1_tc9563_resx_n>;
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pinctrl-names = "default";
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pcie@1,0 {
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reg = <0x40800 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x3 0xff>;
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};
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pcie@2,0 {
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reg = <0x41000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x4 0xff>;
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};
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pcie@3,0 {
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reg = <0x41800 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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bus-range = <0x5 0xff>;
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pci@0,0 {
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reg = <0x50000 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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pci@0,1 {
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reg = <0x50100 0x0 0x0 0x0 0x0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges;
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};
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};
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};
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};
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&tlmm {
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pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
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pins = "gpio78";
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function = "gpio";
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bias-disable;
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input-disable;
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output-enable;
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};
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pcie0_reset_n: pcie0-reset-n-state {
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pins = "gpio87";
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function = "gpio";
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drive-strength = <16>;
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output-low;
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bias-disable;
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};
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pcie0_clkreq_n: pcie0-clkreq-n-state {
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pins = "gpio88";
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function = "pcie0_clkreqn";
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drive-strength = <2>;
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bias-pull-up;
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};
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pcie0_wake_n: pcie0-wake-n-state {
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pins = "gpio89";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
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pins = "gpio124";
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function = "gpio";
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bias-disable;
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input-disable;
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output-enable;
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};
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};
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&wifi {
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status = "disabled";
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};
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