119 lines
2.8 KiB
C
119 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* camss-tpg.h
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*
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* Qualcomm MSM Camera Subsystem - TPG Module
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*
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* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef QC_MSM_CAMSS_TPG_H
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#define QC_MSM_CAMSS_TPG_H
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#include <linux/clk.h>
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#include <linux/bitfield.h>
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#include <media/media-entity.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-mediabus.h>
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#include <media/v4l2-subdev.h>
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#define ENCODE_FORMAT_UNCOMPRESSED_8_BIT 0x1
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#define ENCODE_FORMAT_UNCOMPRESSED_10_BIT 0x2
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#define ENCODE_FORMAT_UNCOMPRESSED_12_BIT 0x3
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#define ENCODE_FORMAT_UNCOMPRESSED_14_BIT 0x4
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#define ENCODE_FORMAT_UNCOMPRESSED_16_BIT 0x5
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#define ENCODE_FORMAT_UNCOMPRESSED_20_BIT 0x6
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#define ENCODE_FORMAT_UNCOMPRESSED_24_BIT 0x7
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#define MSM_TPG_PAD_SRC 0
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#define MSM_TPG_ACTIVE_VC 0
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#define MSM_TPG_ACTIVE_DT 0
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#define TPG_MIN_WIDTH 1
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#define TPG_MIN_HEIGHT 1
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#define TPG_MAX_WIDTH 8191
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#define TPG_MAX_HEIGHT 8191
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#define TPG_GRP_ID 0
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enum tpg_testgen_mode {
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TPG_PAYLOAD_MODE_DISABLED = 0,
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TPG_PAYLOAD_MODE_INCREMENTING = 1,
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TPG_PAYLOAD_MODE_ALTERNATING_55_AA = 2,
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TPG_PAYLOAD_MODE_RANDOM = 5,
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TPG_PAYLOAD_MODE_USER_SPECIFIED = 6,
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TPG_PAYLOAD_MODE_COLOR_BARS = 9,
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TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 = 9,
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};
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struct tpg_testgen_config {
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enum tpg_testgen_mode mode;
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const char * const*modes;
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u8 nmodes;
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};
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struct tpg_format_info {
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u32 code;
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u8 data_type;
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u8 encode_format;
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u8 bpp;
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};
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struct tpg_formats {
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unsigned int nformats;
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const struct tpg_format_info *formats;
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};
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struct tpg_device;
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struct tpg_hw_ops {
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int (*configure_stream)(struct tpg_device *tpg, u8 enable);
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int (*configure_testgen_pattern)(struct tpg_device *tpg, s32 val);
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u32 (*hw_version)(struct tpg_device *tpg);
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int (*reset)(struct tpg_device *tpg);
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void (*subdev_init)(struct tpg_device *tpg);
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};
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struct tpg_subdev_resources {
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u8 lane_cnt;
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const struct tpg_formats *formats;
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const struct tpg_hw_ops *hw_ops;
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};
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struct tpg_device {
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struct camss *camss;
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u8 id;
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struct v4l2_subdev subdev;
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struct media_pad pad;
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void __iomem *base;
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struct camss_clock *clock;
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int nclocks;
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struct tpg_testgen_config testgen;
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struct v4l2_mbus_framefmt fmt;
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struct v4l2_ctrl_handler ctrls;
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struct v4l2_ctrl *testgen_mode;
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const struct tpg_subdev_resources *res;
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u32 hw_version;
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};
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struct camss_subdev_resources;
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const struct tpg_format_info *tpg_get_fmt_entry(const struct tpg_format_info *formats,
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unsigned int nformats,
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u32 code);
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int msm_tpg_subdev_init(struct camss *camss,
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struct tpg_device *tpg,
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const struct camss_subdev_resources *res, u8 id);
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int msm_tpg_register_entity(struct tpg_device *tpg,
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struct v4l2_device *v4l2_dev);
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void msm_tpg_unregister_entity(struct tpg_device *tpg);
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extern const struct tpg_formats tpg_formats_gen1;
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extern const struct tpg_hw_ops tpg_ops_gen1;
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#endif /* QC_MSM_CAMSS_TPG_H */
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