447 lines
13 KiB
C
447 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Phylink and PCS support for MaxLinear MxL862xx switch family
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*
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* Copyright (C) 2024 MaxLinear Inc.
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* Copyright (C) 2025 John Crispin <john@phrozen.org>
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* Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org>
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*/
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#include <linux/bitfield.h>
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#include <linux/mutex.h>
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#include <linux/phylink.h>
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#include <net/dsa.h>
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#include "mxl862xx.h"
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#include "mxl862xx-api.h"
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#include "mxl862xx-cmd.h"
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#include "mxl862xx-host.h"
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#include "mxl862xx-phylink.h"
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void mxl862xx_phylink_get_caps(struct dsa_switch *ds, int port,
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struct phylink_config *config)
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{
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struct mxl862xx_priv *priv = ds->priv;
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config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | MAC_10 |
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MAC_100 | MAC_1000 | MAC_2500FD;
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switch (port) {
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case 1 ... 8:
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__set_bit(PHY_INTERFACE_MODE_INTERNAL,
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config->supported_interfaces);
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break;
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case 9:
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case 13:
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/* Advertised also on old firmware lacking the XPCS API:
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* there the SerDes runs in its flash-configured mode
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* without host control (mac_select_pcs returns NULL),
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* keeping the CPU port working.
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*/
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__set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_2500BASEX, config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_10GKR, config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_USXGMII, config->supported_interfaces);
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fallthrough;
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case 10 ... 12:
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case 14 ... 16:
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if (!MXL862XX_FW_VER_MIN(priv, 1, 0, 84))
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break;
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__set_bit(PHY_INTERFACE_MODE_QSGMII, config->supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_10G_QXGMII, config->supported_interfaces);
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break;
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default:
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break;
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}
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if (port == 9 || port == 13)
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config->mac_capabilities |= MAC_10000FD | MAC_5000FD;
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}
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static struct mxl862xx_pcs *pcs_to_mxl862xx_pcs(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct mxl862xx_pcs, pcs);
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}
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static int mxl862xx_xpcs_if_mode(phy_interface_t interface)
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{
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switch (interface) {
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case PHY_INTERFACE_MODE_SGMII:
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return MXL862XX_XPCS_IF_SGMII;
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case PHY_INTERFACE_MODE_QSGMII:
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return MXL862XX_XPCS_IF_QSGMII;
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case PHY_INTERFACE_MODE_1000BASEX:
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return MXL862XX_XPCS_IF_1000BASEX;
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case PHY_INTERFACE_MODE_2500BASEX:
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return MXL862XX_XPCS_IF_2500BASEX;
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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return MXL862XX_XPCS_IF_USXGMII;
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case PHY_INTERFACE_MODE_10GBASER:
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return MXL862XX_XPCS_IF_10GBASER;
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case PHY_INTERFACE_MODE_10GKR:
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return MXL862XX_XPCS_IF_10GKR;
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default:
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return -EINVAL;
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}
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}
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static int mxl862xx_xpcs_neg_mode(unsigned int neg_mode)
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{
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if (!(neg_mode & PHYLINK_PCS_NEG_INBAND))
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return MXL862XX_XPCS_NEG_NONE;
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if (neg_mode & PHYLINK_PCS_NEG_ENABLED)
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return MXL862XX_XPCS_NEG_INBAND_AN_ON;
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return MXL862XX_XPCS_NEG_INBAND_AN_OFF;
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}
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static int mxl862xx_pcs_enable(struct phylink_pcs *pcs)
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{
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struct mxl862xx_pcs *mpcs = pcs_to_mxl862xx_pcs(pcs);
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/* Bringup is done idempotently by pcs_config; just account this
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* sub-port so pcs_disable powers the shared XPCS down only after
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* the last sub-port has been released.
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*/
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mutex_lock(&mpcs->priv->serdes_lock);
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mpcs->priv->serdes_refcount[mpcs->serdes_id]++;
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mutex_unlock(&mpcs->priv->serdes_lock);
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return 0;
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}
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static void mxl862xx_pcs_disable(struct phylink_pcs *pcs)
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{
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struct mxl862xx_pcs *mpcs = pcs_to_mxl862xx_pcs(pcs);
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struct mxl862xx_xpcs_pcs_disable dis = {};
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struct mxl862xx_priv *priv = mpcs->priv;
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dis.port_id = mpcs->serdes_id;
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/* The SerDes is shared across QSGMII/QUSXGMII sub-ports; only
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* power it down once the last active sub-port goes away. Hold
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* serdes_lock across the count and the power-down so a sibling
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* sub-port enable cannot race the transition to zero.
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*/
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mutex_lock(&priv->serdes_lock);
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if (--priv->serdes_refcount[mpcs->serdes_id] == 0)
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MXL862XX_API_WRITE(priv, MXL862XX_XPCS_PCS_DISABLE, dis);
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mutex_unlock(&priv->serdes_lock);
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}
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/* The XPCS firmware reports failures in the result field using its own
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* libc errno values; ENOTSUP (134) in particular has no kernel errno.
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* Translate the codes the firmware can actually return.
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*/
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static int mxl862xx_xpcs_errno(int result)
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{
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switch (result) {
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case -5: /* firmware -EIO */
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return -EIO;
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case -134: /* firmware -ENOTSUP */
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return -EOPNOTSUPP;
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default: /* firmware -EINVAL and anything unexpected */
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return -EINVAL;
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}
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}
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static int mxl862xx_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct mxl862xx_pcs *mpcs = pcs_to_mxl862xx_pcs(pcs);
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struct mxl862xx_priv *priv = mpcs->priv;
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struct mxl862xx_xpcs_pcs_cfg cfg = {};
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int if_mode, lane, ret, adv;
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if_mode = mxl862xx_xpcs_if_mode(interface);
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if (if_mode < 0) {
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dev_err(priv->ds->dev, "unsupported interface: %s\n",
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phy_modes(interface));
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return if_mode;
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}
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/* The XPCS bringup is per-instance and idempotent in the
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* firmware: every QSGMII/QUSXGMII sub-port may call pcs_config
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* and the firmware will skip the bringup if the requested mode
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* matches the cached one, then update MAC pause for the
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* sub-port indicated by @usx_subport. No serdes_lock is needed
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* here: the refcount held since pcs_enable keeps a sibling
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* pcs_disable from powering the XPCS down, and pcs_disable
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* invalidates the firmware's cached mode so the next pcs_config
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* redoes the bringup.
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*/
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lane = (interface == PHY_INTERFACE_MODE_10G_QXGMII) ?
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MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE;
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cfg.mode = cpu_to_le16(FIELD_PREP(MXL862XX_XPCS_CFG_PORT_ID,
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mpcs->serdes_id) |
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FIELD_PREP(MXL862XX_XPCS_CFG_USX_SUBPORT,
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mpcs->slot) |
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FIELD_PREP(MXL862XX_XPCS_CFG_USX_LANE_MODE, lane) |
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FIELD_PREP(MXL862XX_XPCS_CFG_INTERFACE, if_mode) |
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FIELD_PREP(MXL862XX_XPCS_CFG_NEG_MODE,
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mxl862xx_xpcs_neg_mode(neg_mode)) |
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FIELD_PREP(MXL862XX_XPCS_CFG_ROLE,
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MXL862XX_XPCS_ROLE_MAC) |
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FIELD_PREP(MXL862XX_XPCS_CFG_PERMIT_PAUSE,
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permit_pause_to_mac));
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if (neg_mode & PHYLINK_PCS_NEG_INBAND) {
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adv = phylink_mii_c22_pcs_encode_advertisement(interface,
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advertising);
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if (adv >= 0)
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cfg.advertising.cl37 = cpu_to_le16(adv);
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}
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ret = MXL862XX_API_READ(priv, MXL862XX_XPCS_PCS_CONFIG, cfg);
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if (ret)
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return ret;
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ret = (s16)le16_to_cpu(cfg.result);
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if (ret < 0)
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return mxl862xx_xpcs_errno(ret);
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mpcs->interface = interface;
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return ret > 0 ? 1 : 0;
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}
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static void mxl862xx_pcs_get_state(struct phylink_pcs *pcs,
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unsigned int neg_mode,
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struct phylink_link_state *state)
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{
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struct mxl862xx_pcs *mpcs = pcs_to_mxl862xx_pcs(pcs);
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struct mxl862xx_priv *priv = mpcs->priv;
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struct mxl862xx_xpcs_pcs_state st = {};
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int if_mode, lane, ret;
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u32 mode;
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u16 bmsr;
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if_mode = mxl862xx_xpcs_if_mode(state->interface);
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if (if_mode < 0) {
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state->link = false;
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return;
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}
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lane = (state->interface == PHY_INTERFACE_MODE_10G_QXGMII) ?
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MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE;
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st.mode = cpu_to_le32(FIELD_PREP(MXL862XX_XPCS_ST_PORT_ID,
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mpcs->serdes_id) |
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FIELD_PREP(MXL862XX_XPCS_ST_INTERFACE, if_mode) |
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FIELD_PREP(MXL862XX_XPCS_ST_USX_SUBPORT,
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mpcs->slot) |
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FIELD_PREP(MXL862XX_XPCS_ST_USX_LANE_MODE, lane));
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ret = MXL862XX_API_READ(priv, MXL862XX_XPCS_PCS_GET_STATE, st);
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if (ret) {
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state->link = false;
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return;
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}
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mode = le32_to_cpu(st.mode);
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state->link = FIELD_GET(MXL862XX_XPCS_ST_LINK, mode) &&
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!FIELD_GET(MXL862XX_XPCS_ST_PCS_FAULT, mode);
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state->an_complete = FIELD_GET(MXL862XX_XPCS_ST_AN_COMPLETE, mode);
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switch (state->interface) {
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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bmsr = (state->link ? BMSR_LSTATUS : 0) |
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(state->an_complete ? BMSR_ANEGCOMPLETE : 0);
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phylink_mii_c22_pcs_decode_state(state, neg_mode, bmsr,
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le16_to_cpu(st.lpa.cl37));
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break;
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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if (state->link)
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phylink_decode_usxgmii_word(state,
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le16_to_cpu(st.lpa.usx));
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break;
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case PHY_INTERFACE_MODE_10GBASER:
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case PHY_INTERFACE_MODE_10GKR:
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if (state->link) {
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state->speed = SPEED_10000;
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state->duplex = DUPLEX_FULL;
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}
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break;
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default:
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state->link = false;
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break;
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}
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}
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static void mxl862xx_pcs_an_restart(struct phylink_pcs *pcs)
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{
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struct mxl862xx_pcs *mpcs = pcs_to_mxl862xx_pcs(pcs);
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struct mxl862xx_priv *priv = mpcs->priv;
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struct mxl862xx_xpcs_an_restart an = {};
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int if_mode, lane;
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if_mode = mxl862xx_xpcs_if_mode(mpcs->interface);
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if (if_mode < 0)
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return;
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lane = (mpcs->interface == PHY_INTERFACE_MODE_10G_QXGMII) ?
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MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE;
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an.mode = cpu_to_le16(FIELD_PREP(MXL862XX_XPCS_ANR_PORT_ID,
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mpcs->serdes_id) |
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FIELD_PREP(MXL862XX_XPCS_ANR_INTERFACE, if_mode) |
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FIELD_PREP(MXL862XX_XPCS_ANR_USX_SUBPORT,
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mpcs->slot) |
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FIELD_PREP(MXL862XX_XPCS_ANR_USX_LANE_MODE, lane));
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MXL862XX_API_WRITE(priv, MXL862XX_XPCS_AN_RESTART, an);
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}
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static void mxl862xx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
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phy_interface_t interface, int speed,
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int duplex)
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{
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struct mxl862xx_pcs *mpcs = pcs_to_mxl862xx_pcs(pcs);
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struct mxl862xx_xpcs_pcs_link_up lu = {};
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struct mxl862xx_priv *priv = mpcs->priv;
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int if_mode, lane, dup;
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/* With inband-AN enabled (role=MAC), the XPCS auto-resolves
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* speed/duplex from the partner's AN word and the firmware
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* short-circuits link_up. Skip the firmware round-trip, same
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* as pcs-mtk-lynxi.
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*/
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if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
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return;
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if_mode = mxl862xx_xpcs_if_mode(interface);
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if (if_mode < 0)
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return;
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lane = (interface == PHY_INTERFACE_MODE_10G_QXGMII) ?
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MXL862XX_XPCS_USX_QUAD : MXL862XX_XPCS_USX_SINGLE;
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dup = (duplex == DUPLEX_FULL) ? MXL862XX_XPCS_DUPLEX_FULL :
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MXL862XX_XPCS_DUPLEX_HALF;
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lu.mode = cpu_to_le16(FIELD_PREP(MXL862XX_XPCS_LU_PORT_ID,
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mpcs->serdes_id) |
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FIELD_PREP(MXL862XX_XPCS_LU_INTERFACE, if_mode) |
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FIELD_PREP(MXL862XX_XPCS_LU_USX_SUBPORT,
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mpcs->slot) |
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FIELD_PREP(MXL862XX_XPCS_LU_USX_LANE_MODE, lane) |
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FIELD_PREP(MXL862XX_XPCS_LU_DUPLEX, dup));
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lu.speed = cpu_to_le16(speed);
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MXL862XX_API_WRITE(priv, MXL862XX_XPCS_PCS_LINK_UP, lu);
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}
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static unsigned int mxl862xx_pcs_inband_caps(struct phylink_pcs *pcs,
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phy_interface_t interface)
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{
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switch (interface) {
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_QSGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
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case PHY_INTERFACE_MODE_USXGMII:
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case PHY_INTERFACE_MODE_10G_QXGMII:
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case PHY_INTERFACE_MODE_10GKR:
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return LINK_INBAND_ENABLE;
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case PHY_INTERFACE_MODE_10GBASER:
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return LINK_INBAND_DISABLE;
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default:
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return 0;
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}
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}
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static const struct phylink_pcs_ops mxl862xx_pcs_ops = {
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.pcs_enable = mxl862xx_pcs_enable,
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.pcs_disable = mxl862xx_pcs_disable,
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.pcs_config = mxl862xx_pcs_config,
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.pcs_get_state = mxl862xx_pcs_get_state,
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.pcs_an_restart = mxl862xx_pcs_an_restart,
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.pcs_link_up = mxl862xx_pcs_link_up,
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.pcs_inband_caps = mxl862xx_pcs_inband_caps,
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};
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void mxl862xx_setup_pcs(struct mxl862xx_priv *priv, struct mxl862xx_pcs *pcs,
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int port)
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{
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pcs->priv = priv;
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pcs->serdes_id = MXL862XX_SERDES_PORT_ID(port);
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pcs->slot = MXL862XX_SERDES_SLOT(port);
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pcs->interface = PHY_INTERFACE_MODE_NA;
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pcs->pcs.ops = &mxl862xx_pcs_ops;
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pcs->pcs.poll = true;
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__set_bit(PHY_INTERFACE_MODE_QSGMII, pcs->pcs.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_10G_QXGMII, pcs->pcs.supported_interfaces);
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if (pcs->slot != 0)
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return;
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__set_bit(PHY_INTERFACE_MODE_SGMII, pcs->pcs.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_1000BASEX, pcs->pcs.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_2500BASEX, pcs->pcs.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_10GBASER, pcs->pcs.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_10GKR, pcs->pcs.supported_interfaces);
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__set_bit(PHY_INTERFACE_MODE_USXGMII, pcs->pcs.supported_interfaces);
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}
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static struct phylink_pcs *
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mxl862xx_phylink_mac_select_pcs(struct phylink_config *config,
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phy_interface_t interface)
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{
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struct dsa_port *dp = dsa_phylink_to_port(config);
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struct mxl862xx_priv *priv = dp->ds->priv;
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int port = dp->index;
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switch (port) {
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case 9 ... 16:
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if (!MXL862XX_FW_VER_MIN(priv, 1, 0, 84)) {
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dev_warn_once(dp->ds->dev,
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"SerDes PCS unsupported on old firmware.\n");
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return NULL;
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}
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return &priv->serdes_ports[port - 9].pcs;
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default:
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return NULL;
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}
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}
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static void mxl862xx_phylink_mac_config(struct phylink_config *config,
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unsigned int mode,
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const struct phylink_link_state *state)
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{
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}
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static void mxl862xx_phylink_mac_link_down(struct phylink_config *config,
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unsigned int mode,
|
|
phy_interface_t interface)
|
|
{
|
|
}
|
|
|
|
static void mxl862xx_phylink_mac_link_up(struct phylink_config *config,
|
|
struct phy_device *phydev,
|
|
unsigned int mode,
|
|
phy_interface_t interface,
|
|
int speed, int duplex,
|
|
bool tx_pause, bool rx_pause)
|
|
{
|
|
}
|
|
|
|
const struct phylink_mac_ops mxl862xx_phylink_mac_ops = {
|
|
.mac_config = mxl862xx_phylink_mac_config,
|
|
.mac_link_down = mxl862xx_phylink_mac_link_down,
|
|
.mac_link_up = mxl862xx_phylink_mac_link_up,
|
|
.mac_select_pcs = mxl862xx_phylink_mac_select_pcs,
|
|
};
|