43 lines
1.3 KiB
C
43 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2025, Intel Corporation. */
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#ifndef _ICE_TSPLL_H_
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#define _ICE_TSPLL_H_
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/**
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* struct ice_tspll_params_e82x - E82X TSPLL parameters
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* @refclk_pre_div: Reference clock pre-divisor
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* @post_pll_div: Post PLL divisor
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* @feedback_div: Feedback divisor
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* @frac_n_div: Fractional divisor
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*
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* Clock Generation Unit parameters used to program the PLL based on the
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* selected TIME_REF/TCXO frequency.
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*/
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struct ice_tspll_params_e82x {
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u8 refclk_pre_div;
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u8 post_pll_div;
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u8 feedback_div;
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u32 frac_n_div;
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};
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#define ICE_CGU_NET_REF_CLK0 0x0
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#define ICE_CGU_REF_CLK_BYP0 0x5
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#define ICE_CGU_REF_CLK_BYP0_DIV 0x0
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#define ICE_CGU_REF_CLK_BYP1 0x4
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#define ICE_CGU_REF_CLK_BYP1_DIV 0x1
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#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
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#define ICE_TSPLL_NDIVRATIO_E825 5
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#define ICE_TSPLL_FBDIV_INTGR_E825 256
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int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
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int ice_tspll_init(struct ice_hw *hw);
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int ice_tspll_bypass_mux_active_e825c(struct ice_hw *hw, u8 port, bool *active,
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enum ice_synce_clk output);
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int ice_tspll_cfg_bypass_mux_e825c(struct ice_hw *hw, bool ena, u32 port_num,
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enum ice_synce_clk output);
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int ice_tspll_cfg_synce_ethdiv_e825c(struct ice_hw *hw,
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enum ice_synce_clk output);
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#endif /* _ICE_TSPLL_H_ */
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