70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
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#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
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/* NW_GCC clocks */
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#define NW_GCC_ACMU_MUX_CLK 0
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#define NW_GCC_CAMERA_AHB_CLK 1
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#define NW_GCC_CAMERA_HF_AXI_CLK 2
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#define NW_GCC_CAMERA_SF_AXI_CLK 3
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#define NW_GCC_CAMERA_TRIG_CLK 4
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#define NW_GCC_CAMERA_XO_CLK 5
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#define NW_GCC_DISP_0_AHB_CLK 6
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#define NW_GCC_DISP_0_HF_AXI_CLK 7
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#define NW_GCC_DISP_0_TRIG_CLK 8
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#define NW_GCC_DISP_1_AHB_CLK 9
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#define NW_GCC_DISP_1_HF_AXI_CLK 10
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#define NW_GCC_DISP_1_TRIG_CLK 11
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#define NW_GCC_DPRX0_AXI_HF_CLK 12
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#define NW_GCC_DPRX0_CFG_AHB_CLK 13
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#define NW_GCC_DPRX1_AXI_HF_CLK 14
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#define NW_GCC_DPRX1_CFG_AHB_CLK 15
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#define NW_GCC_EVA_AHB_CLK 16
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#define NW_GCC_EVA_AXI0_CLK 17
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#define NW_GCC_EVA_AXI0C_CLK 18
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#define NW_GCC_EVA_TRIG_CLK 19
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#define NW_GCC_EVA_XO_CLK 20
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#define NW_GCC_FRQ_MEASURE_REF_CLK 21
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#define NW_GCC_GP1_CLK 22
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#define NW_GCC_GP1_CLK_SRC 23
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#define NW_GCC_GP2_CLK 24
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#define NW_GCC_GP2_CLK_SRC 25
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#define NW_GCC_GPLL0 26
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#define NW_GCC_GPLL0_OUT_EVEN 27
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#define NW_GCC_GPU_2_CFG_AHB_CLK 28
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#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29
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#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30
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#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31
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#define NW_GCC_GPU_CFG_AHB_CLK 32
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#define NW_GCC_GPU_GPLL0_CLK_SRC 33
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#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34
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#define NW_GCC_GPU_HSCNOC_GFX_CLK 35
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#define NW_GCC_GPU_SMMU_VOTE_CLK 36
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#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37
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#define NW_GCC_HSCNOC_GPU_AXI_CLK 38
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#define NW_GCC_MMU_1_TCU_VOTE_CLK 39
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#define NW_GCC_VIDEO_AHB_CLK 40
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#define NW_GCC_VIDEO_AXI0_CLK 41
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#define NW_GCC_VIDEO_AXI0C_CLK 42
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#define NW_GCC_VIDEO_AXI1_CLK 43
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#define NW_GCC_VIDEO_XO_CLK 44
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/* NW_GCC power domains */
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/* NW_GCC resets */
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#define NW_GCC_CAMERA_BCR 0
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#define NW_GCC_DISPLAY_0_BCR 1
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#define NW_GCC_DISPLAY_1_BCR 2
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#define NW_GCC_DPRX0_BCR 3
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#define NW_GCC_DPRX1_BCR 4
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#define NW_GCC_EVA_BCR 5
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#define NW_GCC_GPU_2_BCR 6
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#define NW_GCC_GPU_BCR 7
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#define NW_GCC_VIDEO_BCR 8
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#endif
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