245 lines
14 KiB
JSON
245 lines
14 KiB
JSON
[
|
|
{
|
|
"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe6",
|
|
"EventName": "BACLEARS.ANY",
|
|
"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of BACLEARS due to a conditional jump.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe6",
|
|
"EventName": "BACLEARS.COND",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of BACLEARS due to an indirect branch.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe6",
|
|
"EventName": "BACLEARS.INDIRECT",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of BACLEARS due to a return branch.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe6",
|
|
"EventName": "BACLEARS.RETURN",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe6",
|
|
"EventName": "BACLEARS.UNCOND",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.ALL",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.BRANCH_DETECT",
|
|
"PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.BRANCH_RESTEER",
|
|
"PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x40"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.CISC",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long ms flow Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.DECODE",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.ICACHE",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x20"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.ITLB_MISS",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.OTHER",
|
|
"PublicDescription": "Counts the number of instruction retired tagged after a wasted issue slot if none of the previous events occurred Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x80"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc6",
|
|
"EventName": "FRONTEND_RETIRED.PREDECODE",
|
|
"PublicDescription": "Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L2_HIT",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 cache.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L2_MISS",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 cache. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0xe"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x6"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and did not have to snoop another core.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT_NO_SNOOP",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and did not have to snoop another core. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and required a snoop (that resulted in a snoop miss, snoop hitm, snoop hit with fwd, or snoop hit with no fwd).",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT_WITH_SNOOP",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and required a snoop (that resulted in a snoop miss, snoop hitm, snoop hit with fwd, or snoop hit with no fwd). Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 and L3 caches.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ICACHE_L3_MISS",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 and L3 caches. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x8"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x10"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS",
|
|
"PublicDescription": "Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x20"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss, that matched a current outstanding prefetch request initiated by a Code SWPF stream.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xc9",
|
|
"EventName": "FRONTEND_RETIRED_SOURCE.LATE_SWPF",
|
|
"PublicDescription": "Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss, that matched a current outstanding prefetch request initiated by a Code SWPF stream. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x40"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x80",
|
|
"EventName": "ICACHE.ACCESSES",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x3"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x80",
|
|
"EventName": "ICACHE.HIT",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. -",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x80",
|
|
"EventName": "ICACHE.MISSES",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x2"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe7",
|
|
"EventName": "MS_DECODED.MS_BUSY",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xe7",
|
|
"EventName": "MS_DECODED.MS_ENTRY",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x1"
|
|
}
|
|
]
|