65 lines
3.2 KiB
JSON
65 lines
3.2 KiB
JSON
[
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{
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"BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.HARDWARE",
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"PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists.",
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"SampleAfterValue": "100003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "ASSISTS.PAGE_FAULT",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.PAGE_FAULT",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe4",
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"EventName": "LBR_INSERTS.ANY",
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"PublicDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to MISC_RETIRED.LBR_INSERTS] Available PDIST counters: 0,1",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts streaming stores that have any type of response.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10800",
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"PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the total number of BTCLEARS.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xe8",
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"EventName": "PREDICTION.BTCLEAR",
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"PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Cycles the uncore cannot take further requests",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"CounterMask": "1",
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"EventCode": "0x2d",
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"EventName": "XQ.FULL",
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"PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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}
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]
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