105 lines
2.3 KiB
YAML
105 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/imx/fsl,imx53-tve.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX53 Television Encoder (TVE)
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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description:
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The Television Encoder (TVE) is a hardware block in the i.MX53 SoC that
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converts digital video data into analog TV signals (NTSC/PAL).
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properties:
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compatible:
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const: fsl,imx53-tve
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: TVE gate clock
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- description: Display interface selector clock
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clock-names:
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items:
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- const: tve
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- const: di_sel
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ddc-i2c-bus:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the I2C bus used for DDC (Display Data Channel) communication
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to read EDID information from the connected display.
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dac-supply:
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description:
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Regulator supply for the TVE DAC (Digital-to-Analog Converter).
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fsl,tve-mode:
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$ref: /schemas/types.yaml#/definitions/string
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description:
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TVE output mode selection.
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enum:
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- ntsc
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- pal
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- vga
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fsl,hsync-pin:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Pin number for horizontal sync signal in VGA mode.
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minimum: 0
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maximum: 8
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fsl,vsync-pin:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Pin number for vertical sync signal in VGA mode.
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minimum: 0
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maximum: 8
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Port node with one endpoint connected to the IPU display interface.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- fsl,tve-mode
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx5-clock.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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tve@63ff0000 {
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compatible = "fsl,imx53-tve";
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reg = <0x63ff0000 0x1000>;
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interrupts = <92>;
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clocks = <&clks IMX5_CLK_TVE_GATE>,
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<&clks IMX5_CLK_IPU_DI1_SEL>;
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clock-names = "tve", "di_sel";
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fsl,tve-mode = "vga";
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port {
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endpoint {
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remote-endpoint = <&ipu_di1_tve>;
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};
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};
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};
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