189 lines
7.1 KiB
YAML
189 lines
7.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-interrupt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1)
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description: |
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The ASPEED AST2700 SoC integrates two interrupt controller designs:
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- INTC0: Primary controller that routes interrupt sources to upstream,
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processor-specific interrupt controllers
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- INTC1: Secondary controller whose interrupt outputs feed into INTC0
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The SoC contains four processors to which interrupts can be routed:
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- PSP: Primary Service Processor (Cortex-A35)
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- SSP: Secondary Service Processor (Cortex-M4)
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- TSP: Tertiary Service Processor (Cortex-M4)
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- BMCU: Boot MCU (a RISC-V microcontroller)
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The following diagram illustrates the overall architecture of the
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ASPEED AST2700 interrupt controllers:
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+-----------+ +-----------+
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| INTC0 | | INTC1(0) |
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+-----------+ +-----------+
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| Router | +-----------+ | Router |
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| out int | +Peripheral + | out int |
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+-----------+ | 0 0 <-+Controllers+ | INTM | +-----------+
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|PSP GIC <-|---+ . . | +-----------+ | . . <-+Peripheral +
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+-----------+ | . . | | . . | +Controllers+
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+-----------+ | . . | | . . | +-----------+
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|SSP NVIC <-|---+ . . <----------------+ . . |
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+-----------+ | . . | | . . |
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+-----------+ | . . <-------- | . . |
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|TSP NVIC <-|---+ . . | | ----+ . . |
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+-----------+ | . . | | | | O P |
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| . . | | | +-----------+
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| . . <---- | --------------------
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| . . | | | +-----------+ |
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| M N | | ---------+ INTC1(1) | |
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+-----------+ | +-----------+ |
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| . |
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| +-----------+ |
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-------------+ INTC1(N) | |
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+-----------+ |
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+--------------+ |
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+ BMCU APLIC <-+---------------------------------------------
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+--------------+
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INTC0 supports:
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- 128 local peripheral interrupt inputs
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- Fan-in from up to three INTC1 instances via banked interrupt lines (INTM)
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- Local peripheral interrupt outputs
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- Merged interrupt outputs
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- Software interrupt outputs (SWINT)
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- Configurable interrupt routes targeting the PSP, SSP, and TSP
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INTC1 supports:
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- 192 local peripheral interrupt inputs
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- Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank)
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- Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU
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One INTC1 instance is always present, on the SoC's IO die. A further two
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instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS
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Tunneling Protocol & Interface).
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Interrupt numbering model
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-------------------------
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The binding uses a controller-local numbering model. Peripheral device
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nodes use the INTCx local interrupt number (hwirq) in their 'interrupts' or
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'interrupts-extended' properties.
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For AST2700, INTC0 exposes the following (inclusive) input ranges:
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- 000..479: Independent interrupts
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- 480..489: INTM0-INTM9
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- 490..499: INTM10-INTM19
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- 500..509: INTM20-INTM29
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- 510..519: INTM30-INTM39
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- 520..529: INTM40-INTM49
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INTC0's (inclusive) output ranges are as follows:
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- 000..127: 1:1 local peripheral interrupt output to PSP
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- 144..151: Software interrupts from the SSP output to PSP
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- 152..159: Software interrupts from the TSP output to PSP
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- 192..201: INTM0-INTM9 banked outputs to PSP
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- 208..217: INTM30-INTM39 banked outputs to PSP
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- 224..233: INTM40-INTM49 banked outputs to PSP
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- 256..383: 1:1 local peripheral interrupt output to SSP
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- 384..393: INTM10-INTM19 banked outputs to SSP
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- 400..407: Software interrupts from the PSP output to SSP
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- 408..415: Software interrupts from the TSP output to SSP
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- 426..553: 1:1 local peripheral interrupt output to TSP
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- 554..563: INTM20-INTM29 banked outputs to TSP
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- 570..577: Software interrupts from the PSP output to TSP
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- 578..585: Software interrupts from the SSP output to TSP
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Inputs and outputs for INTC1 instances are context-dependent. However, for the
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first instance of INTC1, the (inclusive) output ranges are:
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- 00..05: INTM0-INTM5
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- 10..15: INTM10-INTM15
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- 20..25: INTM20-INTM25
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- 30..35: INTM30-INTM35
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- 40..45: INTM40-INTM45
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- 50..50: BootMCU
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maintainers:
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- Ryan Chen <ryan_chen@aspeedtech.com>
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- Andrew Jeffery <andrew@codeconstruct.com.au>
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properties:
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compatible:
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enum:
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- aspeed,ast2700-intc0
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- aspeed,ast2700-intc1
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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description: Single cell encoding the INTC local interrupt number (hwirq).
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aspeed,interrupt-ranges:
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description: |
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Describes how ranges of controller output pins are routed to a parent
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interrupt controller.
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Each range entry is encoded as:
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<out count phandle parent-specifier...>
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where:
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- out: First controller interrupt output index in the range.
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- count: Number of consecutive controller interrupt outputs and parent
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interrupt inputs in this range.
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- phandle: Phandle to the parent interrupt controller node.
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- parent-specifier: Interrupt specifier, as defined by the parent
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interrupt controller binding.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 3
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items:
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description: Range descriptors with a parent interrupt specifier.
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- aspeed,interrupt-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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interrupt-controller@12100000 {
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compatible = "aspeed,ast2700-intc0";
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reg = <0x12100000 0x3b00>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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#interrupt-cells = <1>;
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aspeed,interrupt-ranges =
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<0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
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<256 128 &ssp_nvic 0 0>,
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<384 10 &ssp_nvic 160 0>,
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<400 8 &ssp_nvic 144 0>,
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<408 8 &ssp_nvic 152 0>,
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<426 128 &tsp_nvic 0 0>,
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<554 10 &tsp_nvic 160 0>,
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<570 8 &tsp_nvic 144 0>,
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<578 8 &tsp_nvic 152 0>;
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};
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