308 lines
7.6 KiB
YAML
308 lines
7.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/rockchip,rk3568-vicap.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip RK3568 Video Capture (VICAP)
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maintainers:
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- Michael Riesch <michael.riesch@collabora.com>
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description:
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The Rockchip RK3568 Video Capture (VICAP) block features a digital video
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port (DVP, a parallel video interface) and a MIPI CSI-2 port. It receives
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the data from camera sensors, video decoders, or other companion ICs and
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transfers it into system main memory by AXI bus.
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The Rockchip RK3588 Video Capture (VICAP) is similar to its RK3568
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counterpart, but features six MIPI CSI-2 ports and additional connections
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to the image signal processor (ISP) blocks.
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properties:
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compatible:
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enum:
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- rockchip,rk3568-vicap
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- rockchip,rk3588-vicap
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 4
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maxItems: 5
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clock-names:
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items:
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- const: aclk
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- const: hclk
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- const: dclk
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- const: iclk
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- const: iclk1
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minItems: 4
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iommus:
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maxItems: 1
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resets:
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minItems: 5
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maxItems: 9
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reset-names:
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minItems: 5
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maxItems: 9
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Phandle to general register file used for video input block control.
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power-domains:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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additionalProperties: false
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: The digital video port (DVP, a parallel video interface).
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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bus-type:
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enum:
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- 5 # MEDIA_BUS_TYPE_PARALLEL
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- 6 # MEDIA_BUS_TYPE_BT656
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rockchip,dvp-clk-delay:
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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minimum: 0
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maximum: 127
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description:
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Delay the DVP path clock input to align the sampling phase,
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only valid in dual edge sampling mode. Delay is zero by
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default and can be adjusted optionally.
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required:
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- bus-type
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the MIPI CSI-2 receiver 0 output.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the MIPI CSI-2 receiver 1 output.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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port@3:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the MIPI CSI-2 receiver 2 output.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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port@4:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the MIPI CSI-2 receiver 3 output.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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port@5:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the MIPI CSI-2 receiver 4 output.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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port@6:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the MIPI CSI-2 receiver 5 output.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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port@10:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the ISP0 input.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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port@11:
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$ref: /schemas/graph.yaml#/properties/port
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description: Port connected to the ISP1 input.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- ports
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: rockchip,rk3568-vicap
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then:
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properties:
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clocks:
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maxItems: 4
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clock-names:
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maxItems: 4
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resets:
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maxItems: 5
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reset-names:
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items:
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- const: arst
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- const: hrst
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- const: drst
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- const: prst
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- const: irst
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ports:
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properties:
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port@2: false
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port@3: false
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port@4: false
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port@5: false
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port@6: false
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port@10: false
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port@11: false
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- if:
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properties:
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compatible:
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contains:
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const: rockchip,rk3588-vicap
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then:
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properties:
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clocks:
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minItems: 5
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clock-names:
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minItems: 5
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resets:
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minItems: 9
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reset-names:
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items:
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- const: arst
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- const: hrst
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- const: drst
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- const: irst0
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- const: irst1
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- const: irst2
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- const: irst3
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- const: irst4
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- const: irst5
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3568-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/rk3568-power.h>
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#include <dt-bindings/media/video-interfaces.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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vicap: video-capture@fdfe0000 {
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compatible = "rockchip,rk3568-vicap";
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reg = <0x0 0xfdfe0000 0x0 0x200>;
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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assigned-clocks = <&cru DCLK_VICAP>;
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assigned-clock-rates = <300000000>;
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clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>,
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<&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>;
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clock-names = "aclk", "hclk", "dclk", "iclk";
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iommus = <&vicap_mmu>;
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power-domains = <&power RK3568_PD_VI>;
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resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>,
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<&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>,
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<&cru SRST_I_VICAP>;
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reset-names = "arst", "hrst", "drst", "prst", "irst";
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rockchip,grf = <&grf>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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vicap_dvp: port@0 {
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reg = <0>;
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vicap_dvp_input: endpoint {
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bus-type = <MEDIA_BUS_TYPE_BT656>;
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bus-width = <16>;
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pclk-sample = <MEDIA_PCLK_SAMPLE_DUAL_EDGE>;
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remote-endpoint = <&it6801_output>;
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};
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};
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vicap_mipi: port@1 {
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reg = <1>;
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vicap_mipi_input: endpoint {
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remote-endpoint = <&csi_output>;
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};
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};
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};
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};
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};
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