140 lines
2.8 KiB
YAML
140 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Lynx 10G SerDes PHY
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maintainers:
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- Vladimir Oltean <vladimir.oltean@nxp.com>
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description:
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The 10G Lynx is a multi-protocol SerDes block which handles networking, PCIe,
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SATA and other high-speed interfaces. It is present on most QorIQ and
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Layerscape SoCs. The register map is common, but the integration is
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SoC-specific, with the differences consisting in register endianness, the
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number of lanes, protocol converters available per lane and their location in
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the PCCR registers. Some SoCs have multiple SerDes blocks and those differ in
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their protocol capabilities per lane.
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properties:
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compatible:
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enum:
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- fsl,ls1028a-serdes
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- fsl,ls1046a-serdes1
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- fsl,ls1046a-serdes2
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- fsl,ls1088a-serdes1
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- fsl,ls1088a-serdes2
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- fsl,ls2088a-serdes1
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- fsl,ls2088a-serdes2
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reg:
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maxItems: 1
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big-endian: true
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"#phy-cells":
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const: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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patternProperties:
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"^phy@[0-7]$":
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type: object
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description: SerDes lane (single RX/TX differential pair)
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properties:
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reg:
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minimum: 0
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maximum: 7
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description: Lane index as seen in register map
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"#phy-cells":
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const: 0
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required:
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- reg
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- "#phy-cells"
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#phy-cells"
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- "#address-cells"
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- "#size-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,ls1028a-serdes
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- fsl,ls1046a-serdes1
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- fsl,ls1046a-serdes2
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- fsl,ls1088a-serdes1
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- fsl,ls1088a-serdes2
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then:
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patternProperties:
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"^phy@[0-7]$":
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properties:
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reg:
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minimum: 0
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maximum: 3
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- if:
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properties:
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compatible:
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enum:
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- fsl,ls1046a-serdes1
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- fsl,ls1046a-serdes2
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then:
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required:
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- big-endian
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else:
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properties:
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big-endian: false
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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serdes@1ea0000 {
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compatible = "fsl,ls1028a-serdes";
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reg = <0x0 0x1ea0000 0x0 0xffff>;
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#address-cells = <1>;
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#size-cells = <0>;
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#phy-cells = <1>;
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phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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phy@2 {
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reg = <2>;
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#phy-cells = <0>;
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};
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phy@3 {
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reg = <3>;
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#phy-cells = <0>;
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};
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};
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};
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