103 lines
3.9 KiB
YAML
103 lines
3.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra238 AON Pinmux Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra238-pinmux-aon
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reg:
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maxItems: 1
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patternProperties:
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"^pinmux(-[a-z0-9-]+)?$":
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type: object
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# pin groups
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additionalProperties:
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$ref: nvidia,tegra238-pinmux-common.yaml
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properties:
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nvidia,pins:
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items:
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enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
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pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
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soc_gpio25_paa6, soc_gpio26_paa7,
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hdmi_cec_pbb0,
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spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
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spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
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uart3_rx_pcc6, gen2_i2c_scl_pcc7,
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gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
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gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
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dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
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pwm3_pee0, pwm7_pee1, soc_gpio49_pee2,
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soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5,
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soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2,
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soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5,
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soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0,
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soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3,
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uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6,
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uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1,
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uart5_cts_phh2, soc_gpio86_phh3,
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# drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH)
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drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
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drive_vcomp_alert_paa2, drive_pwm1_paa3,
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drive_batt_oc_paa4, drive_soc_gpio04_paa5,
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drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
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drive_hdmi_cec_pbb0,
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drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
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drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
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drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
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drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
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drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
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drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
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drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
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drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
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drive_pwm3_pee0, drive_pwm7_pee1,
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drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,
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drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,
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drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,
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drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,
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drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,
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drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,
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drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,
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drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0,
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drive_uart5_tx_pgg7, drive_uart5_rx_phh0,
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drive_uart2_tx_pgg2, drive_uart2_rx_pgg3,
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drive_uart2_cts_pgg5, drive_uart2_rts_pgg4,
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drive_uart5_cts_phh2, drive_uart5_rts_phh1 ]
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/pinctrl-tegra.h>
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pinmux@c300000 {
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compatible = "nvidia,tegra238-pinmux-aon";
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reg = <0x0c300000 0x4000>;
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pinctrl-names = "cec";
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pinctrl-0 = <&cec_state>;
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cec_state: pinmux-cec {
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cec {
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nvidia,pins = "hdmi_cec_pbb0";
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nvidia,function = "hdmi_cec";
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};
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};
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};
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...
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