145 lines
4.7 KiB
YAML
145 lines
4.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Eliza TLMM block
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maintainers:
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- Abel Vesa <abel.vesa@oss.qualcomm.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,eliza-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 93
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gpio-line-names:
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maxItems: 185
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-eliza-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-eliza-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-eliza-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$"
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- enum: [ ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
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audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl,
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cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx,
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coex_uart2_rx, coex_uart2_tx, dbg_out_clk,
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ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
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ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio,
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gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1,
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hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1,
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hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec,
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host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
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ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out,
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mdp_vsync, mdp_vsync0_out, mdp_vsync11_out,
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mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
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mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3,
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pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
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pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk,
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qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
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qlink_big_request, qlink_little_enable,
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qlink_little_request, qlink_wmss, qspi0, qspi_clk,
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qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira,
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qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb,
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qup1_se3, qup1_se4_01, qup1_se4_23,
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qup1_se5, qup1_se6, qup1_se6_l1_mira,
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qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb,
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qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb,
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qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1,
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qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb,
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qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5,
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qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1,
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sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2,
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tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
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tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
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uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
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uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy,
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vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,eliza-tlmm";
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reg = <0x0f100000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 186>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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qup-uart14-default-state {
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pins = "gpio18", "gpio19";
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function = "qup2_se5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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...
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