124 lines
3.5 KiB
YAML
124 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Shikra TLMM block
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maintainers:
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- Komal Bajaj <komal.bajaj@oss.qualcomm.com>
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description: |
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Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,shikra-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 83
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gpio-line-names:
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maxItems: 166
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-shikra-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-shikra-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-shikra-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$"
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- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
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sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,
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atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,
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cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,
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dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,
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emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,
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emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,
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i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,
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mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,
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nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,
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phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,
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qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,
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qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,
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qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,
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qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,
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ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,
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tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,
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vfr, vsense_trigger_mirnat, wlan ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@500000 {
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compatible = "qcom,shikra-tlmm";
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reg = <0x00500000 0x800000>;
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 166>;
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qup-uart0-default-state {
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pins = "gpio0", "gpio1";
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function = "qup0_se1";
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drive-strength = <2>;
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bias-disable;
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};
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};
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...
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