114 lines
3.4 KiB
YAML
114 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Audio Front End PCM controller for MT8196
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maintainers:
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- Darren Ye <darren.ye@mediatek.com>
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properties:
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compatible:
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const: mediatek,mt8196-afe
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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memory-region:
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maxItems: 1
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: mux for audio intbus
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- description: mux for audio engen1
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- description: mux for audio engen2
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- description: mux for audio h
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- description: audio apll1 clock
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- description: audio apll2 clock
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- description: audio apll12 divide for i2sin0
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- description: audio apll12 divide for i2sin1
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- description: audio apll12 divide for fmi2s
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- description: audio apll12 divide for tdmout mck
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- description: audio apll12 divide for tdmout bck
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- description: mux for adsp clock
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clock-names:
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items:
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- const: top_aud_intbus
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- const: top_aud_eng1
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- const: top_aud_eng2
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- const: top_aud_h
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- const: apll1
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- const: apll2
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- const: apll12_div_i2sin0
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- const: apll12_div_i2sin1
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- const: apll12_div_fmi2s
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- const: apll12_div_tdmout_m
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- const: apll12_div_tdmout_b
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- const: top_adsp
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required:
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- compatible
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- reg
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- interrupts
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- memory-region
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- power-domains
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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afe@1a110000 {
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compatible = "mediatek,mt8196-afe";
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reg = <0 0x1a110000 0 0x9000>;
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interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>;
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memory-region = <&afe_dma_mem_reserved>;
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power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO
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pinctrl-names = "default";
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pinctrl-0 = <&aud_pins_default>;
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clocks = <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL
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<&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL
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<&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL
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<&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL
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<&vlp_cksys_clk 0>, //CLK_VLP_CK_VLP_APLL1
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<&vlp_cksys_clk 1>, //CLK_VLP_CK_VLP_APLL2
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<&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0
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<&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1
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<&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S
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<&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M
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<&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B
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<&cksys_clk 45>; //CLK_CK_ADSP_SEL
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clock-names = "top_aud_intbus",
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"top_aud_eng1",
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"top_aud_eng2",
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"top_aud_h",
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"apll1",
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"apll2",
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"apll12_div_i2sin0",
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"apll12_div_i2sin1",
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"apll12_div_fmi2s",
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"apll12_div_tdmout_m",
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"apll12_div_tdmout_b",
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"top_adsp";
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};
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};
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...
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