138 lines
4.1 KiB
YAML
138 lines
4.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/renesas,fsi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas FIFO-buffered Serial Interface (FSI)
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maintainers:
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- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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properties:
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$nodename:
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pattern: "^sound@.*"
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compatible:
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oneOf:
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# for FSI2 SoC
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- items:
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- enum:
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- renesas,fsi2-sh73a0 # SH-Mobile AG5
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- renesas,fsi2-r8a7740 # R-Mobile A1
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- enum:
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- renesas,sh_fsi2
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# for Generic
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- items:
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- enum:
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- renesas,sh_fsi
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- renesas,sh_fsi2
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: Main FSI module clock
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- description: |
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SPU bus/bridge clock. On R8A7740, this clock must be enabled to allow
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register access as the FSI block is connected behind the SPU bus.
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- description: CPG DIV6 functional clocks for FSI port A
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- description: CPG DIV6 functional clocks for FSI port B
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- description: FSI dividers for port A used for audio clock generation
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- description: FSI dividers for port B used for audio clock generation
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- description: External clock inputs for FSI port A provided by the board
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- description: External clock inputs for FSI port B provided by the board
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clock-names:
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minItems: 1
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maxItems: 8
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items:
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enum:
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- fck # Main FSI module clock
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- spu # optional SPU bus/bridge clock
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- icka # optional CPG DIV6 functional clocks for FSI port A
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- ickb # optional CPG DIV6 functional clocks for FSI port B
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- diva # optional FSI dividers for port A used for audio clock generation
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- divb # optional FSI dividers for port B used for audio clock generation
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- xcka # optional External clock inputs for FSI port A provided by the board
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- xckb # optional External clock inputs for FSI port B provided by the board
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power-domains:
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maxItems: 1
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'#sound-dai-cells':
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const: 1
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patternProperties:
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"^fsi(a|b),spdif-connection$":
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$ref: /schemas/types.yaml#/definitions/flag
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description: FSI is connected by S/PDIF
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"^fsi(a|b),stream-mode-support$":
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$ref: /schemas/types.yaml#/definitions/flag
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description: FSI supports 16bit stream mode
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"^fsi(a|b),use-internal-clock$":
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$ref: /schemas/types.yaml#/definitions/flag
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description: FSI uses internal clock when master mode
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- power-domains
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- '#sound-dai-cells'
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unevaluatedProperties: false
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allOf:
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- $ref: dai-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: renesas,fsi2-r8a7740
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then:
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required:
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- clock-names
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properties:
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clock-names:
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minItems: 2
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items:
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- const: fck
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- const: spu
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- enum: [icka, ickb, diva, divb, xcka, xckb]
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- enum: [icka, ickb, diva, divb, xcka, xckb]
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- enum: [icka, ickb, diva, divb, xcka, xckb]
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- enum: [icka, ickb, diva, divb, xcka, xckb]
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- enum: [icka, ickb, diva, divb, xcka, xckb]
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- enum: [icka, ickb, diva, divb, xcka, xckb]
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examples:
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- |
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#include <dt-bindings/clock/r8a7740-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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sh_fsi2: sound@fe1f0000 {
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compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
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reg = <0xfe1f0000 0x400>;
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interrupts = <GIC_SPI 9 0x4>;
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clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>,
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<&fsia_clk>, <&fsiack_clk>, <&fsidiva_clk>,
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<&fsib_clk>, <&fsibck_clk>, <&fsidivb_clk>;
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clock-names = "fck", "spu", "icka", "xcka", "diva",
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"ickb", "xckb", "divb";
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power-domains = <&pd_a4mp>;
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#sound-dai-cells = <1>;
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fsia,spdif-connection;
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fsia,stream-mode-support;
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fsia,use-internal-clock;
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};
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