240 lines
6.2 KiB
Devicetree
240 lines
6.2 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2026 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rv1103b";
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interrupt-parent = <&gic>;
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&cru ARMCLK>;
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device_type = "cpu";
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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clock-frequency = <24000000>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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xin24m: oscillator-24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rv1103b-pinctrl";
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rockchip,grf = <&ioc>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpio0: gpio@20520000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20520000 0x200>;
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clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
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gpio-controller;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@20d80000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20d80000 0x200>;
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clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
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gpio-controller;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@20840000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20840000 0x200>;
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clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
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gpio-controller;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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cru: clock-controller@20000000 {
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compatible = "rockchip,rv1103b-cru";
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reg = <0x20000000 0x81000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pmu_grf: syscon@20160000 {
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compatible = "rockchip,rv1103b-pmu-grf", "syscon", "simple-mfd";
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reg = <0x20160000 0x1000>;
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reboot_mode: reboot-mode {
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compatible = "syscon-reboot-mode";
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offset = <0x200>;
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mode-normal = <BOOT_NORMAL>;
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mode-recovery = <BOOT_RECOVERY>;
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mode-bootloader = <BOOT_FASTBOOT>;
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mode-loader = <BOOT_BL_DOWNLOAD>;
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};
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};
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ioc: syscon@20170000 {
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compatible = "rockchip,rv1103b-ioc", "syscon";
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reg = <0x20170000 0x60000>;
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};
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gic: interrupt-controller@20411000 {
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compatible = "arm,gic-400";
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reg = <0x20411000 0x1000>,
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<0x20412000 0x2000>,
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<0x20414000 0x2000>,
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<0x20416000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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};
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uart0: serial@20540000 {
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compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
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reg = <0x20540000 0x100>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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sdmmc1: mmc@20650000 {
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compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc";
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reg = <0x20650000 0x4000>;
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clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <150000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
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status = "disabled";
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};
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uart1: serial@20870000 {
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compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
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reg = <0x20870000 0x100>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@20880000 {
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compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart";
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reg = <0x20880000 0x100>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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sdmmc0: mmc@20d20000 {
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compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc";
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reg = <0x20d20000 0x4000>;
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clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <150000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc0_det &sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4>;
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status = "disabled";
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};
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emmc: mmc@20d30000 {
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compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3576-dw-mshc";
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reg = <0x20d30000 0x4000>;
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clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <150000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus4>;
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status = "disabled";
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};
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fspi0: spi@20d40000 {
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compatible = "rockchip,sfc";
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reg = <0x20d40000 0x4000>;
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clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>;
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clock-names = "clk_sfc", "hclk_sfc";
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&fspi_bus4 &fspi_cs0 &fspi_clk>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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system_sram: sram@210f6000 {
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compatible = "mmio-sram";
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reg = <0x210f6000 0x8000>;
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ranges = <0 0x210f6000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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#include "rv1103b-pinctrl.dtsi"
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