195 lines
4.0 KiB
Devicetree
195 lines
4.0 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* Device Tree Source for AST27xx SoC Family
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*
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* Copyright (C) 2026 ASPEED Technology Inc.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "aspeed,ast2700";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x2>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x3>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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};
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};
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secondary {
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#address-cells = <1>;
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#size-cells = <0>;
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ssp_nvic: interrupt-controller@e000e100 {
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compatible = "arm,v7m-nvic";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe000e100>;
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arm,num-irq-priority-bits = <3>;
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status = "disabled";
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};
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};
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tertiary {
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#address-cells = <1>;
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#size-cells = <0>;
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tsp_nvic: interrupt-controller@e000e100 {
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compatible = "arm,v7m-nvic";
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#interrupt-cells = <2>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0xe000e100>;
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arm,num-irq-priority-bits = <3>;
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status = "disabled";
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};
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};
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bootmcu {
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bootmcu_hlic: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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status = "disabled";
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};
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};
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firmware {
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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atf: trusted-firmware-a@430000000 {
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reg = <0x4 0x30000000 0x0 0x80000>;
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no-map;
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};
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optee_core: optee-core@430080000 {
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reg = <0x4 0x30080000 0x0 0x1000000>;
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no-map;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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arm,cpu-registers-not-fw-configured;
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always-on;
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};
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gic: interrupt-controller@12200000 {
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compatible = "arm,gic-v3";
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reg = <0 0x12200000 0 0x10000>, /* GICD */
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<0 0x12280000 0 0x80000>, /* GICR */
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<0 0x40440000 0 0x1000>; /* GICC */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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soc0: bus@10000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x4000000>;
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};
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soc1: bus@14000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x14000000 0x0 0x14000000 0x2 0xec000000>;
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};
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};
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#include "aspeed-g7-soc0.dtsi"
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#include "aspeed-g7-soc1.dtsi"
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