116 lines
2.1 KiB
Devicetree
116 lines
2.1 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Axis ARTPEC-9 SoC pin-mux and pin-config device tree source
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*
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* Copyright (c) 2025 Samsung Electronics Co., Ltd.
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* https://www.samsung.com
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* Copyright (c) 2025 Axis Communications AB.
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* https://www.axis.com
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*/
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#include "artpec-pinctrl.h"
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&pinctrl_fsys0 {
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gpe0: gpe0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe1: gpe1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe2: gpe2-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe3: gpe3-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpe4: gpe4-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf0: gpf0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpf1: gpf1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpi0: gpi0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gps0: gps0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gps1: gps1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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&pinctrl_fsys1 {
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gpu0: gpu0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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serial0_bus: serial0-bus-pins {
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samsung,pins = "gpu0-0", "gpu0-1";
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samsung,pin-function = <ARTPEC_PIN_FUNC_2>;
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samsung,pin-pud = <ARTPEC_PIN_PULL_UP>;
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samsung,pin-drv = <ARTPEC_PIN_DRV_SR3>;
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};
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};
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&pinctrl_peric {
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gpa0: gpa0-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpa1: gpa1-gpio-bank {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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