32 lines
831 B
Devicetree
32 lines
831 B
Devicetree
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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&ddr_pmu0 {
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compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu";
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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};
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&ddr_subsys {
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db_pmu0: db-pmu@5ca40000 {
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compatible = "fsl,imx8dxl-db-pmu";
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reg = <0x5ca40000 0x10000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_4>, <&db_pmu0_lpcg IMX_LPCG_CLK_0>;
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clock-names = "ipg", "cnt";
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};
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db_pmu0_lpcg: clock-controller@5cae0000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5cae0000 0x10000>;
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#clock-cells = <1>;
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clocks = <&db_ipg_clk>, <&db_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
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clock-output-names = "perf_lpcg_cnt_clk",
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"perf_lpcg_ipg_clk";
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power-domains = <&pd IMX_SC_R_PERF>;
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};
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};
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