130 lines
2.8 KiB
Devicetree
130 lines
2.8 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2025 NXP
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*/
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#include "imx91-pinfunc.h"
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#include "imx91_93_common.dtsi"
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/{
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thermal-zones {
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu>;
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trips {
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cpu_alert: cpu-alert {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu-crit {
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temperature = <90000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert>;
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cooling-device =
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<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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};
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&aips1 {
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tmu: thermal-sensor@44482000 {
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compatible = "fsl,imx91-tmu";
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reg = <0x44482000 0x1000>;
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#thermal-sensor-cells = <0>;
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clocks = <&clk IMX93_CLK_TMC_GATE>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "thr1", "thr2", "ready";
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nvmem-cells = <&tmu_trim1>, <&tmu_trim2>;
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nvmem-cell-names = "trim1", "trim2";
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};
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};
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&clk {
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compatible = "fsl,imx91-ccm";
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};
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&ddr_pmu {
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compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";
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};
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&eqos {
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clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
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<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
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<&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET1_QOS_TSN>,
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<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
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assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET1_QOS_TSN>;
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assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
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<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
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assigned-clock-rates = <100000000>, <250000000>;
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};
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&fec {
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clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
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<&clk IMX91_CLK_ENET2_REGULAR_GATE>,
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<&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET2_REGULAR>,
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<&clk IMX93_CLK_DUMMY>;
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assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
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<&clk IMX91_CLK_ENET2_REGULAR>;
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assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
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<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
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assigned-clock-rates = <100000000>, <250000000>;
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};
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&i3c1 {
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clocks = <&clk IMX93_CLK_BUS_AON>,
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<&clk IMX93_CLK_I3C1_GATE>,
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<&clk IMX93_CLK_DUMMY>;
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};
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&i3c2 {
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clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
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<&clk IMX93_CLK_I3C2_GATE>,
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<&clk IMX93_CLK_DUMMY>;
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};
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&iomuxc {
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compatible = "fsl,imx91-iomuxc";
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};
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&media_blk_ctrl {
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compatible = "fsl,imx91-media-blk-ctrl", "syscon";
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clocks = <&clk IMX93_CLK_MEDIA_APB>,
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<&clk IMX93_CLK_MEDIA_AXI>,
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<&clk IMX93_CLK_NIC_MEDIA_GATE>,
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<&clk IMX93_CLK_MEDIA_DISP_PIX>,
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<&clk IMX93_CLK_CAM_PIX>,
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<&clk IMX93_CLK_LCDIF_GATE>,
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<&clk IMX93_CLK_ISI_GATE>,
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<&clk IMX93_CLK_MIPI_CSI_GATE>;
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clock-names = "apb", "axi", "nic", "disp", "cam",
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"lcdif", "isi", "csi";
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};
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&ocotp {
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tmu_trim1: tmu-trim@a0 {
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reg = <0xa0 0x4>;
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};
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tmu_trim2: tmu-trim@a4 {
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reg = <0xa4 0x4>;
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};
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};
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