45 lines
1.0 KiB
C
45 lines
1.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright 2025 NXP
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*/
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#ifndef __IMX952_POWER_H__
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#define __IMX952_POWER_H__
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#define IMX952_PD_ANA 0
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#define IMX952_PD_AON 1
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#define IMX952_PD_BBSM 2
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#define IMX952_PD_CAMERA 3
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#define IMX952_PD_CCMSRCGPC 4
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#define IMX952_PD_A55C0 5
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#define IMX952_PD_A55C1 6
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#define IMX952_PD_A55C2 7
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#define IMX952_PD_A55C3 8
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#define IMX952_PD_A55P 9
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#define IMX952_PD_DDR 10
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#define IMX952_PD_DISPLAY 11
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#define IMX952_PD_GPU 12
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#define IMX952_PD_HSIO_TOP 13
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#define IMX952_PD_HSIO_WAON 14
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#define IMX952_PD_M7 15
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#define IMX952_PD_NETC 16
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#define IMX952_PD_NOC 17
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#define IMX952_PD_NPU 18
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#define IMX952_PD_VPU 19
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#define IMX952_PD_WAKEUP 20
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#define IMX952_PERF_M33 0
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#define IMX952_PERF_WAKEUP 1
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#define IMX952_PERF_M7 2
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#define IMX952_PERF_DRAM 3
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#define IMX952_PERF_HSIO 4
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#define IMX952_PERF_NPU 5
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#define IMX952_PERF_NOC 6
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#define IMX952_PERF_A55 7
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#define IMX952_PERF_GPU 8
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#define IMX952_PERF_VPU 9
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#define IMX952_PERF_CAM 10
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#define IMX952_PERF_DISP 11
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#endif
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