534 lines
15 KiB
Devicetree
534 lines
15 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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#include <dt-bindings/clock/mediatek,mt7981-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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/ {
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compatible = "mediatek,mt7981b";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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oscillator-40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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#clock-cells = <0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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wo_boot: wo-boot@15194000 {
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reg = <0 0x15194000 0 0x1000>;
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no-map;
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};
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wo_ilm0: wo-ilm@151e0000 {
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reg = <0 0x151e0000 0 0x8000>;
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no-map;
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};
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wo_dlm0: wo-dlm@151e8000 {
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reg = <0 0x151e8000 0 0x2000>;
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no-map;
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};
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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no-map;
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};
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wmcpu_emi: wmcpu-reserved@47c80000 {
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reg = <0 0x47c80000 0 0x100000>;
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no-map;
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};
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wo_emi0: wo-emi@47d80000 {
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reg = <0 0x47d80000 0 0x40000>;
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no-map;
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};
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wo_data: wo-data@47dc0000 {
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reg = <0 0x47dc0000 0 0x240000>;
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no-map;
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};
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};
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soc {
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compatible = "simple-bus";
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>; /* GICR */
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt7981-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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topckgen: clock-controller@1001b000 {
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compatible = "mediatek,mt7981-topckgen", "syscon";
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reg = <0 0x1001b000 0 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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};
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apmixedsys: clock-controller@1001e000 {
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compatible = "mediatek,mt7981-apmixedsys";
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reg = <0 0x1001e000 0 0x1000>;
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#clock-cells = <1>;
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};
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0 0x10048000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_PWM_STA>,
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<&infracfg CLK_INFRA_PWM_HCK>,
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<&infracfg CLK_INFRA_PWM1_CK>,
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<&infracfg CLK_INFRA_PWM2_CK>,
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<&infracfg CLK_INFRA_PWM3_CK>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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#pwm-cells = <2>;
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
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reg = <0 0x10060000 0 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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crypto@10320000 {
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compatible = "mediatek,mt7981-crypto",
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"inside-secure,safexcel-eip97ies";
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reg = <0 0x10320000 0 0x40000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ring0", "ring1", "ring2", "ring3";
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clocks = <&topckgen CLK_TOP_EIP97B>;
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clock-names = "core";
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assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x100>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uart", "wakeup";
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clocks = <&infracfg CLK_INFRA_UART0_SEL>,
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<&infracfg CLK_INFRA_UART0_CK>;
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clock-names = "baud", "bus";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x100>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uart", "wakeup";
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clocks = <&infracfg CLK_INFRA_UART1_SEL>,
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<&infracfg CLK_INFRA_UART1_CK>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x100>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uart", "wakeup";
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clocks = <&infracfg CLK_INFRA_UART2_SEL>,
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<&infracfg CLK_INFRA_UART2_CK>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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i2c@11007000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11007000 0 0x1000>,
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<0 0x10217080 0 0x80>;
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_I2C0_CK>,
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<&infracfg CLK_INFRA_AP_DMA_CK>,
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<&infracfg CLK_INFRA_I2C_MCK_CK>,
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<&infracfg CLK_INFRA_I2C_PCK_CK>;
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clock-names = "main", "dma", "arb", "pmic";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@11009000 {
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compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x11009000 0 0x1000>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI2_CK>,
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<&infracfg CLK_INFRA_SPI2_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi@1100a000 {
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compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x1100a000 0 0x1000>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI0_CK>,
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<&infracfg CLK_INFRA_SPI0_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi@1100b000 {
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compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
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reg = <0 0x1100b000 0 0x1000>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI1_CK>,
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<&infracfg CLK_INFRA_SPI1_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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thermal@1100c800 {
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compatible = "mediatek,mt7981-thermal",
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"mediatek,mt7986-thermal";
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reg = <0 0x1100c800 0 0x800>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_THERM_CK>,
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<&infracfg CLK_INFRA_ADC_26M_CK>;
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clock-names = "therm", "auxadc";
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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#thermal-sensor-cells = <1>;
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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};
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auxadc: adc@1100d000 {
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compatible = "mediatek,mt7981-auxadc",
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"mediatek,mt7986-auxadc";
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reg = <0 0x1100d000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
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clock-names = "main";
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#io-channel-cells = <1>;
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status = "disabled";
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};
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xhci: usb@11200000 {
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compatible = "mediatek,mt7986-xhci", "mediatek,mtk-xhci";
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reg = <0 0x11200000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
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reg-names = "mac", "ippc";
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clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
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<&infracfg CLK_INFRA_IUSB_CK>,
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<&infracfg CLK_INFRA_IUSB_133_CK>,
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<&infracfg CLK_INFRA_IUSB_66M_CK>,
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<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
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clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
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status = "disabled";
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};
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pcie: pcie@11280000 {
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compatible = "mediatek,mt7981-pcie",
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"mediatek,mt8192-pcie";
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reg = <0 0x11280000 0 0x4000>;
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reg-names = "pcie-mac";
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ranges = <0x82000000 0 0x20000000
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0x0 0x20000000 0 0x10000000>;
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bus-range = <0x00 0xff>;
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clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
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<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
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<&infracfg CLK_INFRA_IPCIER_CK>,
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<&infracfg CLK_INFRA_IPCIEB_CK>;
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clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
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device_type = "pci";
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phys = <&u3port0 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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status = "disabled";
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pio: pinctrl@11d00000 {
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compatible = "mediatek,mt7981-pinctrl";
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reg = <0 0x11d00000 0 0x1000>,
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<0 0x11c00000 0 0x1000>,
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<0 0x11c10000 0 0x1000>,
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<0 0x11d20000 0 0x1000>,
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<0 0x11e00000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x11f10000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
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"iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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gpio-ranges = <&pio 0 0 57>;
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gpio-controller;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0";
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};
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};
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};
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topmisc: topmisc@11d10000 {
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compatible = "mediatek,mt7981-topmisc", "syscon";
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reg = <0 0x11d10000 0 0x10000>;
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#clock-cells = <1>;
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};
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usb_phy: t-phy@11e10000 {
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compatible = "mediatek,mt7981-tphy",
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"mediatek,generic-tphy-v2";
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ranges = <0 0 0x11e10000 0x1700>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "disabled";
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u2port0: usb-phy@0 {
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reg = <0x0 0x700>;
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clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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u3port0: usb-phy@700 {
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reg = <0x700 0x900>;
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clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
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clock-names = "ref";
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#phy-cells = <1>;
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mediatek,syscon-type = <&topmisc 0x218 0>;
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};
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};
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efuse@11f20000 {
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compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
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reg = <0 0x11f20000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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soc-uuid@140 {
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reg = <0x140 0x10>;
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};
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thermal_calibration: thermal-calib@274 {
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reg = <0x274 0xc>;
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};
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phy_calibration: phy-calib@8dc {
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reg = <0x8dc 0x10>;
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};
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};
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ethsys: clock-controller@15000000 {
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compatible = "mediatek,mt7981-ethsys", "syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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wed: wed@15010000 {
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compatible = "mediatek,mt7981-wed",
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"syscon";
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reg = <0 0x15010000 0 0x1000>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
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<&wo_data>, <&wo_boot>;
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memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
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"wo-data", "wo-boot";
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mediatek,wo-ccif = <&wo_ccif0>;
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};
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eth: ethernet@15100000 {
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compatible = "mediatek,mt7981-eth";
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reg = <0 0x15100000 0 0x40000>;
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assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
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<&topckgen CLK_TOP_SGM_325M_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
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<&topckgen CLK_TOP_CB_SGM_325M>;
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clocks = <ðsys CLK_ETH_FE_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_WOCPU0_EN>,
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<&topckgen CLK_TOP_SGM_REG>,
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<&sgmiisys0 CLK_SGM0_TX_EN>,
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<&sgmiisys0 CLK_SGM0_RX_EN>,
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<&sgmiisys0 CLK_SGM0_CK0_EN>,
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<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
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<&sgmiisys1 CLK_SGM1_TX_EN>,
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<&sgmiisys1 CLK_SGM1_RX_EN>,
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<&sgmiisys1 CLK_SGM1_CK1_EN>,
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<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
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<&topckgen CLK_TOP_NETSYS_SEL>,
|
|
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
|
|
clock-names = "fe", "gp2", "gp1", "wocpu0",
|
|
"sgmii_ck",
|
|
"sgmii_tx250m", "sgmii_rx250m",
|
|
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
|
"sgmii2_tx250m", "sgmii2_rx250m",
|
|
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
|
"netsys0", "netsys1";
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0",
|
|
"pdma1", "pdma2", "pdma3";
|
|
sram = <ð_sram>;
|
|
mediatek,ethsys = <ðsys>;
|
|
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
|
mediatek,infracfg = <&topmisc>;
|
|
mediatek,wed = <&wed>;
|
|
status = "disabled";
|
|
|
|
mdio_bus: mdio-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
int_gbe_phy: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <0>;
|
|
phy-mode = "gmii";
|
|
phy-is-integrated;
|
|
nvmem-cells = <&phy_calibration>;
|
|
nvmem-cell-names = "phy-cal-data";
|
|
};
|
|
};
|
|
};
|
|
|
|
eth_sram: sram@15140000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0 0x15140000 0 0x40000>;
|
|
ranges = <0 0x15140000 0 0x40000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
|
|
wo_ccif0: syscon@151a5000 {
|
|
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
|
reg = <0 0x151a5000 0 0x1000>;
|
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
wifi: wifi@18000000 {
|
|
compatible = "mediatek,mt7981-wmac";
|
|
reg = <0 0x18000000 0 0x1000000>,
|
|
<0 0x10003000 0 0x1000>,
|
|
<0 0x11d10000 0 0x1000>;
|
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
|
|
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
|
|
clock-names = "mcu", "ap2conn";
|
|
memory-region = <&wmcpu_emi>;
|
|
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
|
|
reset-names = "consys";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|