69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef __DTS_GLYMUR_MAILBOX_IPCC_H
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#define __DTS_GLYMUR_MAILBOX_IPCC_H
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/* Glymur physical client IDs */
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#define IPCC_MPROC_AOP 0
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#define IPCC_MPROC_TZ 1
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#define IPCC_MPROC_MPSS 2
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#define IPCC_MPROC_LPASS 3
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#define IPCC_MPROC_SLPI 4
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#define IPCC_MPROC_SDC 5
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#define IPCC_MPROC_CDSP 6
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#define IPCC_MPROC_NPU 7
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#define IPCC_MPROC_APSS 8
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#define IPCC_MPROC_GPU 9
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#define IPCC_MPROC_ICP 11
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#define IPCC_MPROC_VPU 12
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#define IPCC_MPROC_PCIE0 13
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#define IPCC_MPROC_PCIE1 14
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#define IPCC_MPROC_PCIE2 15
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#define IPCC_MPROC_SPSS 16
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#define IPCC_MPROC_PCIE3 19
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#define IPCC_MPROC_PCIE4 20
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#define IPCC_MPROC_PCIE5 21
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#define IPCC_MPROC_PCIE6 22
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#define IPCC_MPROC_TME 23
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#define IPCC_MPROC_WPSS 24
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#define IPCC_MPROC_PCIE7 44
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#define IPCC_MPROC_SOCCP 46
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#define IPCC_COMPUTE_L0_LPASS 0
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#define IPCC_COMPUTE_L0_CDSP 1
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#define IPCC_COMPUTE_L0_APSS 2
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#define IPCC_COMPUTE_L0_GPU 3
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#define IPCC_COMPUTE_L0_CVP 6
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#define IPCC_COMPUTE_L0_ICP 7
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#define IPCC_COMPUTE_L0_VPU 8
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#define IPCC_COMPUTE_L0_DPU 9
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#define IPCC_COMPUTE_L0_SOCCP 11
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#define IPCC_COMPUTE_L1_LPASS 0
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#define IPCC_COMPUTE_L1_CDSP 1
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#define IPCC_COMPUTE_L1_APSS 2
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#define IPCC_COMPUTE_L1_GPU 3
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#define IPCC_COMPUTE_L1_CVP 6
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#define IPCC_COMPUTE_L1_ICP 7
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#define IPCC_COMPUTE_L1_VPU 8
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#define IPCC_COMPUTE_L1_DPU 9
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#define IPCC_COMPUTE_L1_SOCCP 11
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#define IPCC_PERIPH_LPASS 0
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#define IPCC_PERIPH_APSS 1
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#define IPCC_PERIPH_PCIE0 2
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#define IPCC_PERIPH_PCIE1 3
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#define IPCC_PERIPH_PCIE2 6
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#define IPCC_PERIPH_PCIE3 7
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#define IPCC_PERIPH_PCIE4 8
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#define IPCC_PERIPH_PCIE5 9
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#define IPCC_PERIPH_PCIE6 10
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#define IPCC_PERIPH_PCIE7 11
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#define IPCC_PERIPH_SOCCP 13
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#define IPCC_PERIPH_WPSS 16
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#endif
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