182 lines
4.0 KiB
Devicetree
182 lines
4.0 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
/dts-v1/;
|
|
|
|
#include <dt-bindings/clock/econet,en751221-scu.h>
|
|
|
|
/ {
|
|
compatible = "econet,en751221";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
hpt_clock: clock {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <200000000>; /* 200 MHz */
|
|
};
|
|
|
|
cpus: cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "mips,mips34Kc";
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
cpuintc: interrupt-controller {
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
chip_scu: syscon@1fa20000 {
|
|
compatible = "econet,en751221-chip-scu", "syscon";
|
|
reg = <0x1fa20000 0x388>;
|
|
};
|
|
|
|
pcie_phy1: pcie-phy@1fac0000 {
|
|
compatible = "econet,en751221-pcie-gen2";
|
|
reg = <0x1fac0000 0x1000>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
pcie_phy0: pcie-phy@1faf2000 {
|
|
compatible = "econet,en751221-pcie-gen1";
|
|
reg = <0x1faf2000 0x1000>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
scuclk: clock-controller@1fb00000 {
|
|
compatible = "econet,en751221-scu";
|
|
reg = <0x1fb00000 0x970>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
intc: interrupt-controller@1fb40000 {
|
|
compatible = "econet,en751221-intc";
|
|
reg = <0x1fb40000 0x100>;
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
|
|
};
|
|
|
|
pciecfg: pciecfg@1fb80000 {
|
|
compatible = "mediatek,generic-pciecfg", "syscon";
|
|
reg = <0x1fb80000 0x1000>;
|
|
};
|
|
|
|
pcie0: pcie@1fb81000 {
|
|
compatible = "econet,en7528-pcie";
|
|
device_type = "pci";
|
|
reg = <0x1fb81000 0x1000>;
|
|
reg-names = "port0";
|
|
linux,pci-domain = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <23>;
|
|
interrupt-names = "pcie_irq";
|
|
clocks = <&scuclk EN751221_CLK_PCIE>;
|
|
clock-names = "sys_ck0";
|
|
phys = <&pcie_phy0>;
|
|
phy-names = "pcie-phy0";
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x01000000 0 0x00000000 0x1f600000 0 0x00008000>,
|
|
<0x82000000 0 0x20000000 0x20000000 0 0x08000000>;
|
|
status = "disabled";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
|
<0 0 0 2 &pcie_intc0 1>,
|
|
<0 0 0 3 &pcie_intc0 2>,
|
|
<0 0 0 4 &pcie_intc0 3>;
|
|
|
|
pcie_intc0: interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
slot0: pcie@0,0 {
|
|
reg = <0x0000 0 0 0 0>;
|
|
device_type = "pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@1fb83000 {
|
|
compatible = "econet,en7528-pcie";
|
|
device_type = "pci";
|
|
reg = <0x1fb83000 0x1000>;
|
|
reg-names = "port1";
|
|
linux,pci-domain = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <24>;
|
|
interrupt-names = "pcie_irq";
|
|
clocks = <&scuclk EN751221_CLK_PCIE>;
|
|
clock-names = "sys_ck1";
|
|
phys = <&pcie_phy1>;
|
|
phy-names = "pcie-phy1";
|
|
bus-range = <0x00 0xff>;
|
|
ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>,
|
|
<0x82000000 0 0x28000000 0x28000000 0 0x08000000>;
|
|
status = "disabled";
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
|
<0 0 0 2 &pcie_intc1 1>,
|
|
<0 0 0 3 &pcie_intc1 2>,
|
|
<0 0 0 4 &pcie_intc1 3>;
|
|
|
|
pcie_intc1: interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
};
|
|
|
|
slot1: pcie@1,0 {
|
|
reg = <0x0800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
uart: serial@1fbf0000 {
|
|
compatible = "ns16550";
|
|
reg = <0x1fbf0000 0x30>;
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <0>;
|
|
/*
|
|
* Conversion of baud rate to clock frequency requires a
|
|
* computation that is not in the ns16550 driver, so this
|
|
* uart is fixed at 115200 baud.
|
|
*/
|
|
clock-frequency = <1843200>;
|
|
};
|
|
|
|
timer_hpt: timer@1fbf0400 {
|
|
compatible = "econet,en751221-timer";
|
|
reg = <0x1fbf0400 0x100>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <30>;
|
|
clocks = <&hpt_clock>;
|
|
};
|
|
};
|