1346 lines
36 KiB
Devicetree
1346 lines
36 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
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*/
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#include <dt-bindings/clock/spacemit,k1-syscon.h>
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#include <dt-bindings/phy/phy.h>
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "SpacemiT K1";
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compatible = "spacemit,k1";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <24000000>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_0>;
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};
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core1 {
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cpu = <&cpu_1>;
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};
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core2 {
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cpu = <&cpu_2>;
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};
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core3 {
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cpu = <&cpu_3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_4>;
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};
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core1 {
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cpu = <&cpu_5>;
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};
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core2 {
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cpu = <&cpu_6>;
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};
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core3 {
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cpu = <&cpu_7>;
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};
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};
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};
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cpu_0: cpu@0 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_1: cpu@1 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <1>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu1_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_2: cpu@2 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <2>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu2_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_3: cpu@3 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <3>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster0_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu3_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_4: cpu@4 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <4>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu4_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_5: cpu@5 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <5>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu5_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_6: cpu@6 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <6>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu6_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cpu_7: cpu@7 {
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compatible = "spacemit,x60", "riscv";
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device_type = "cpu";
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reg = <7>;
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riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
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"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
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"zifencei", "zihintpause", "zihpm", "zfh", "zba",
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"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
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"sscofpmf", "sstc", "svinval", "svnapot", "svpbmt";
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riscv,cbom-block-size = <64>;
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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i-cache-block-size = <64>;
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i-cache-size = <32768>;
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i-cache-sets = <128>;
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d-cache-block-size = <64>;
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d-cache-size = <32768>;
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d-cache-sets = <128>;
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next-level-cache = <&cluster1_l2_cache>;
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mmu-type = "riscv,sv39";
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cpu7_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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cluster0_l2_cache: l2-cache0 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <524288>;
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cache-sets = <512>;
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cache-unified;
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};
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cluster1_l2_cache: l2-cache1 {
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compatible = "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-size = <524288>;
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cache-sets = <512>;
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cache-unified;
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};
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};
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clocks {
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vctcxo_1m: clock-1m {
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compatible = "fixed-clock";
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clock-frequency = <1000000>;
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clock-output-names = "vctcxo_1m";
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#clock-cells = <0>;
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};
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vctcxo_24m: clock-24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "vctcxo_24m";
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#clock-cells = <0>;
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};
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vctcxo_3m: clock-3m {
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compatible = "fixed-clock";
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clock-frequency = <3000000>;
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clock-output-names = "vctcxo_3m";
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#clock-cells = <0>;
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};
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osc_32k: clock-32k {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc_32k";
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#clock-cells = <0>;
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};
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};
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thermal-zones {
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soc-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&thermal 0>;
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trips {
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soc-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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package-thermal {
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polling-delay-passive = <0>;
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polling-delay = <0>;
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thermal-sensors = <&thermal 1>;
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trips {
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package-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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gpu-thermal {
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polling-delay-passive = <100>;
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polling-delay = <0>;
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thermal-sensors = <&thermal 2>;
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trips {
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gpu-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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cluster0-thermal {
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polling-delay-passive = <100>;
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polling-delay = <0>;
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thermal-sensors = <&thermal 3>;
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trips {
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cluster0-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cluster0-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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cluster1-thermal {
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polling-delay-passive = <100>;
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polling-delay = <0>;
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thermal-sensors = <&thermal 4>;
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trips {
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cluster1-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cluster1-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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};
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <2>;
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#size-cells = <2>;
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dma-noncoherent;
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ranges;
|
|
|
|
syscon_rcpu: system-controller@c0880000 {
|
|
compatible = "spacemit,k1-syscon-rcpu";
|
|
reg = <0x0 0xc0880000 0x0 0x2048>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
syscon_rcpu2: system-controller@c0888000 {
|
|
compatible = "spacemit,k1-syscon-rcpu2";
|
|
reg = <0x0 0xc0888000 0x0 0x28>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
usbphy2: phy@c0a30000 {
|
|
compatible = "spacemit,k1-usb2-phy";
|
|
reg = <0x0 0xc0a30000 0x0 0x200>;
|
|
clocks = <&syscon_apmu CLK_USB30>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
combo_phy: phy@c0b10000 {
|
|
compatible = "spacemit,k1-combo-phy";
|
|
reg = <0x0 0xc0b10000 0x0 0x1000>;
|
|
clocks = <&vctcxo_24m>,
|
|
<&syscon_apmu CLK_PCIE0_DBI>,
|
|
<&syscon_apmu CLK_PCIE0_MASTER>,
|
|
<&syscon_apmu CLK_PCIE0_SLAVE>;
|
|
clock-names = "refclk",
|
|
"dbi",
|
|
"mstr",
|
|
"slv";
|
|
resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
|
|
<&syscon_apmu RESET_PCIE0_DBI>,
|
|
<&syscon_apmu RESET_PCIE0_MASTER>,
|
|
<&syscon_apmu RESET_PCIE0_SLAVE>;
|
|
reset-names = "phy",
|
|
"dbi",
|
|
"mstr",
|
|
"slv";
|
|
#phy-cells = <1>;
|
|
spacemit,apmu = <&syscon_apmu>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1_phy: phy@c0c10000 {
|
|
compatible = "spacemit,k1-pcie-phy";
|
|
reg = <0x0 0xc0c10000 0x0 0x1000>;
|
|
clocks = <&vctcxo_24m>;
|
|
clock-names = "refclk";
|
|
resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
|
|
reset-names = "phy";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie2_phy: phy@c0d10000 {
|
|
compatible = "spacemit,k1-pcie-phy";
|
|
reg = <0x0 0xc0d10000 0x0 0x1000>;
|
|
clocks = <&vctcxo_24m>;
|
|
clock-names = "refclk";
|
|
resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
|
|
reset-names = "phy";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@d4010800 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd4010800 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI0>,
|
|
<&syscon_apbc CLK_TWSI0_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI0>;
|
|
interrupts = <36>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@d4011000 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd4011000 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI1>,
|
|
<&syscon_apbc CLK_TWSI1_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI1>;
|
|
interrupts = <37>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@d4012000 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd4012000 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI2>,
|
|
<&syscon_apbc CLK_TWSI2_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI2>;
|
|
interrupts = <38>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@d4012800 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd4012800 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI4>,
|
|
<&syscon_apbc CLK_TWSI4_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI4>;
|
|
interrupts = <40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@d4013800 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd4013800 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI5>,
|
|
<&syscon_apbc CLK_TWSI5_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI5>;
|
|
interrupts = <41>;
|
|
status = "disabled";
|
|
};
|
|
|
|
syscon_apbc: system-controller@d4015000 {
|
|
compatible = "spacemit,k1-syscon-apbc";
|
|
reg = <0x0 0xd4015000 0x0 0x1000>;
|
|
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
|
|
<&vctcxo_24m>;
|
|
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
|
|
"vctcxo_24m";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
thermal: thermal@d4018000 {
|
|
compatible = "spacemit,k1-tsensor";
|
|
reg = <0x0 0xd4018000 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_TSEN>,
|
|
<&syscon_apbc CLK_TSEN_BUS>;
|
|
clock-names = "core", "bus";
|
|
interrupts = <61>;
|
|
resets = <&syscon_apbc RESET_TSEN>;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
i2c6: i2c@d4018800 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd4018800 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI6>,
|
|
<&syscon_apbc CLK_TWSI6_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI6>;
|
|
interrupts = <70>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio: gpio@d4019000 {
|
|
compatible = "spacemit,k1-gpio";
|
|
reg = <0x0 0xd4019000 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_GPIO>,
|
|
<&syscon_apbc CLK_GPIO_BUS>;
|
|
clock-names = "core", "bus";
|
|
gpio-controller;
|
|
#gpio-cells = <3>;
|
|
interrupts = <58>;
|
|
interrupt-parent = <&plic>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
gpio-ranges = <&pinctrl 0 0 0 32>,
|
|
<&pinctrl 1 0 32 32>,
|
|
<&pinctrl 2 0 64 32>,
|
|
<&pinctrl 3 0 96 32>;
|
|
};
|
|
|
|
pwm0: pwm@d401a000 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401a000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM0>;
|
|
resets = <&syscon_apbc RESET_PWM0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@d401a400 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401a400 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM1>;
|
|
resets = <&syscon_apbc RESET_PWM1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@d401a800 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401a800 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM2>;
|
|
resets = <&syscon_apbc RESET_PWM2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@d401ac00 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401ac00 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM3>;
|
|
resets = <&syscon_apbc RESET_PWM3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@d401b000 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401b000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM4>;
|
|
resets = <&syscon_apbc RESET_PWM4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm5: pwm@d401b400 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401b400 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM5>;
|
|
resets = <&syscon_apbc RESET_PWM5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@d401b800 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401b800 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM6>;
|
|
resets = <&syscon_apbc RESET_PWM6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@d401bc00 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd401bc00 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM7>;
|
|
resets = <&syscon_apbc RESET_PWM7>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@d401d000 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd401d000 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI7>,
|
|
<&syscon_apbc CLK_TWSI7_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI7>;
|
|
interrupts = <18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@d401d800 {
|
|
compatible = "spacemit,k1-i2c";
|
|
reg = <0x0 0xd401d800 0x0 0x38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_TWSI8>,
|
|
<&syscon_apbc CLK_TWSI8_BUS>;
|
|
clock-names = "func", "bus";
|
|
clock-frequency = <400000>;
|
|
resets = <&syscon_apbc RESET_TWSI8>;
|
|
interrupts = <19>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl@d401e000 {
|
|
compatible = "spacemit,k1-pinctrl";
|
|
reg = <0x0 0xd401e000 0x0 0x1000>;
|
|
clocks = <&syscon_apbc CLK_AIB>,
|
|
<&syscon_apbc CLK_AIB_BUS>;
|
|
clock-names = "func", "bus";
|
|
spacemit,apbc = <&syscon_apbc>;
|
|
};
|
|
|
|
pwm8: pwm@d4020000 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4020000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM8>;
|
|
resets = <&syscon_apbc RESET_PWM8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm9: pwm@d4020400 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4020400 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM9>;
|
|
resets = <&syscon_apbc RESET_PWM9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm10: pwm@d4020800 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4020800 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM10>;
|
|
resets = <&syscon_apbc RESET_PWM10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm11: pwm@d4020c00 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4020c00 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM11>;
|
|
resets = <&syscon_apbc RESET_PWM11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm12: pwm@d4021000 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4021000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM12>;
|
|
resets = <&syscon_apbc RESET_PWM12>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm13: pwm@d4021400 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4021400 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM13>;
|
|
resets = <&syscon_apbc RESET_PWM13>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm14: pwm@d4021800 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4021800 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM14>;
|
|
resets = <&syscon_apbc RESET_PWM14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm15: pwm@d4021c00 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4021c00 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM15>;
|
|
resets = <&syscon_apbc RESET_PWM15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm16: pwm@d4022000 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4022000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM16>;
|
|
resets = <&syscon_apbc RESET_PWM16>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm17: pwm@d4022400 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4022400 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM17>;
|
|
resets = <&syscon_apbc RESET_PWM17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm18: pwm@d4022800 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4022800 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM18>;
|
|
resets = <&syscon_apbc RESET_PWM18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm19: pwm@d4022c00 {
|
|
compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
|
|
reg = <0x0 0xd4022c00 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&syscon_apbc CLK_PWM19>;
|
|
resets = <&syscon_apbc RESET_PWM19>;
|
|
status = "disabled";
|
|
};
|
|
|
|
syscon_mpmu: system-controller@d4050000 {
|
|
compatible = "spacemit,k1-syscon-mpmu";
|
|
reg = <0x0 0xd4050000 0x0 0x209c>;
|
|
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
|
|
<&vctcxo_24m>;
|
|
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
|
|
"vctcxo_24m";
|
|
#clock-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
pll: clock-controller@d4090000 {
|
|
compatible = "spacemit,k1-pll";
|
|
reg = <0x0 0xd4090000 0x0 0x1000>;
|
|
clocks = <&vctcxo_24m>;
|
|
spacemit,mpmu = <&syscon_mpmu>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
syscon_apmu: system-controller@d4282800 {
|
|
compatible = "spacemit,k1-syscon-apmu";
|
|
reg = <0x0 0xd4282800 0x0 0x400>;
|
|
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
|
|
<&vctcxo_24m>;
|
|
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
|
|
"vctcxo_24m";
|
|
#clock-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
plic: interrupt-controller@e0000000 {
|
|
compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
|
|
reg = <0x0 0xe0000000 0x0 0x4000000>;
|
|
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
|
|
<&cpu1_intc 11>, <&cpu1_intc 9>,
|
|
<&cpu2_intc 11>, <&cpu2_intc 9>,
|
|
<&cpu3_intc 11>, <&cpu3_intc 9>,
|
|
<&cpu4_intc 11>, <&cpu4_intc 9>,
|
|
<&cpu5_intc 11>, <&cpu5_intc 9>,
|
|
<&cpu6_intc 11>, <&cpu6_intc 9>,
|
|
<&cpu7_intc 11>, <&cpu7_intc 9>;
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
riscv,ndev = <159>;
|
|
};
|
|
|
|
clint: timer@e4000000 {
|
|
compatible = "spacemit,k1-clint", "sifive,clint0";
|
|
reg = <0x0 0xe4000000 0x0 0x10000>;
|
|
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
|
|
<&cpu1_intc 3>, <&cpu1_intc 7>,
|
|
<&cpu2_intc 3>, <&cpu2_intc 7>,
|
|
<&cpu3_intc 3>, <&cpu3_intc 7>,
|
|
<&cpu4_intc 3>, <&cpu4_intc 7>,
|
|
<&cpu5_intc 3>, <&cpu5_intc 7>,
|
|
<&cpu6_intc 3>, <&cpu6_intc 7>,
|
|
<&cpu7_intc 3>, <&cpu7_intc 7>;
|
|
};
|
|
|
|
syscon_apbc2: system-controller@f0610000 {
|
|
compatible = "spacemit,k1-syscon-apbc2";
|
|
reg = <0x0 0xf0610000 0x0 0x20>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
/* sec_i2c3: 0xf0614000, not available from Linux */
|
|
|
|
camera-bus {
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
|
<0x0 0x80000000 0x1 0x00000000 0x1 0x80000000>;
|
|
};
|
|
|
|
dma-bus {
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
|
<0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>;
|
|
|
|
pdma: dma-controller@d4000000 {
|
|
compatible = "spacemit,k1-pdma";
|
|
reg = <0x0 0xd4000000 0x0 0x4000>;
|
|
clocks = <&syscon_apmu CLK_DMA>;
|
|
resets = <&syscon_apmu RESET_DMA>;
|
|
interrupts = <72>;
|
|
dma-channels = <16>;
|
|
#dma-cells= <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@d4017000 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017000 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART0>,
|
|
<&syscon_apbc CLK_UART0_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART0>;
|
|
interrupts = <42>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@d4017100 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017100 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART2>,
|
|
<&syscon_apbc CLK_UART2_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART2>;
|
|
interrupts = <44>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@d4017200 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017200 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART3>,
|
|
<&syscon_apbc CLK_UART3_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART3>;
|
|
interrupts = <45>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@d4017300 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017300 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART4>,
|
|
<&syscon_apbc CLK_UART4_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART4>;
|
|
interrupts = <46>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@d4017400 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017400 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART5>,
|
|
<&syscon_apbc CLK_UART5_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART5>;
|
|
interrupts = <47>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@d4017500 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017500 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART6>,
|
|
<&syscon_apbc CLK_UART6_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART6>;
|
|
interrupts = <48>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@d4017600 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017600 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART7>,
|
|
<&syscon_apbc CLK_UART7_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART7>;
|
|
interrupts = <49>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart8: serial@d4017700 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017700 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART8>,
|
|
<&syscon_apbc CLK_UART8_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART8>;
|
|
interrupts = <50>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart9: serial@d4017800 {
|
|
compatible = "spacemit,k1-uart",
|
|
"intel,xscale-uart";
|
|
reg = <0x0 0xd4017800 0x0 0x100>;
|
|
clocks = <&syscon_apbc CLK_UART9>,
|
|
<&syscon_apbc CLK_UART9_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_UART9>;
|
|
interrupts = <51>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qspi: spi@d420c000 {
|
|
compatible = "spacemit,k1-qspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0xd420c000 0x0 0x1000>,
|
|
<0x0 0xb8000000 0x0 0xc00000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
clocks = <&syscon_apmu CLK_QSPI_BUS>,
|
|
<&syscon_apmu CLK_QSPI>;
|
|
clock-names = "qspi_en", "qspi";
|
|
resets = <&syscon_apmu RESET_QSPI>,
|
|
<&syscon_apmu RESET_QSPI_BUS>;
|
|
interrupts = <117>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@d401c000 {
|
|
compatible = "spacemit,k1-spi";
|
|
reg = <0x0 0xd401c000 0x0 0x30>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&syscon_apbc CLK_SSP3>,
|
|
<&syscon_apbc CLK_SSP3_BUS>;
|
|
clock-names = "core", "bus";
|
|
resets = <&syscon_apbc RESET_SSP3>;
|
|
interrupts = <55>;
|
|
dmas = <&pdma 20>, <&pdma 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* sec_uart1: 0xf0612000, not available from Linux */
|
|
};
|
|
|
|
multimedia-bus {
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
|
<0x0 0x80000000 0x1 0x00000000 0x3 0x80000000>;
|
|
};
|
|
|
|
network-bus {
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
|
<0x0 0x80000000 0x1 0x00000000 0x0 0x80000000>;
|
|
|
|
eth0: ethernet@cac80000 {
|
|
compatible = "spacemit,k1-emac";
|
|
reg = <0x0 0xcac80000 0x0 0x420>;
|
|
clocks = <&syscon_apmu CLK_EMAC0_BUS>;
|
|
interrupts = <131>;
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
resets = <&syscon_apmu RESET_EMAC0>;
|
|
spacemit,apmu = <&syscon_apmu 0x3e4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
eth1: ethernet@cac81000 {
|
|
compatible = "spacemit,k1-emac";
|
|
reg = <0x0 0xcac81000 0x0 0x420>;
|
|
clocks = <&syscon_apmu CLK_EMAC1_BUS>;
|
|
interrupts = <133>;
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
resets = <&syscon_apmu RESET_EMAC1>;
|
|
spacemit,apmu = <&syscon_apmu 0x3ec>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pcie-bus {
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
|
|
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
|
|
|
|
pcie0: pcie@ca000000 {
|
|
device_type = "pci";
|
|
compatible = "spacemit,k1-pcie";
|
|
reg = <0x0 0xca000000 0x0 0x00001000>,
|
|
<0x0 0xca300000 0x0 0x0001ff24>,
|
|
<0x0 0x8f000000 0x0 0x00002000>,
|
|
<0x0 0xc0b20000 0x0 0x00001000>;
|
|
reg-names = "dbi",
|
|
"atu",
|
|
"config",
|
|
"link";
|
|
linux,pci-domain = <0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
|
|
interrupts = <141>;
|
|
interrupt-names = "msi";
|
|
clocks = <&syscon_apmu CLK_PCIE0_DBI>,
|
|
<&syscon_apmu CLK_PCIE0_MASTER>,
|
|
<&syscon_apmu CLK_PCIE0_SLAVE>;
|
|
clock-names = "dbi",
|
|
"mstr",
|
|
"slv";
|
|
resets = <&syscon_apmu RESET_PCIE0_DBI>,
|
|
<&syscon_apmu RESET_PCIE0_MASTER>,
|
|
<&syscon_apmu RESET_PCIE0_SLAVE>;
|
|
reset-names = "dbi",
|
|
"mstr",
|
|
"slv";
|
|
spacemit,apmu = <&syscon_apmu 0x03cc>;
|
|
status = "disabled";
|
|
|
|
pcie0_port: pcie@0 {
|
|
device_type = "pci";
|
|
compatible = "pciclass,0604";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@ca400000 {
|
|
device_type = "pci";
|
|
compatible = "spacemit,k1-pcie";
|
|
reg = <0x0 0xca400000 0x0 0x00001000>,
|
|
<0x0 0xca700000 0x0 0x0001ff24>,
|
|
<0x0 0x9f000000 0x0 0x00002000>,
|
|
<0x0 0xc0c20000 0x0 0x00001000>;
|
|
reg-names = "dbi",
|
|
"atu",
|
|
"config",
|
|
"link";
|
|
linux,pci-domain = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
|
|
<0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
|
|
interrupts = <142>;
|
|
interrupt-names = "msi";
|
|
clocks = <&syscon_apmu CLK_PCIE1_DBI>,
|
|
<&syscon_apmu CLK_PCIE1_MASTER>,
|
|
<&syscon_apmu CLK_PCIE1_SLAVE>;
|
|
clock-names = "dbi",
|
|
"mstr",
|
|
"slv";
|
|
resets = <&syscon_apmu RESET_PCIE1_DBI>,
|
|
<&syscon_apmu RESET_PCIE1_MASTER>,
|
|
<&syscon_apmu RESET_PCIE1_SLAVE>;
|
|
reset-names = "dbi",
|
|
"mstr",
|
|
"slv";
|
|
spacemit,apmu = <&syscon_apmu 0x3d4>;
|
|
status = "disabled";
|
|
|
|
pcie1_port: pcie@0 {
|
|
device_type = "pci";
|
|
compatible = "pciclass,0604";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
|
|
pcie2: pcie@ca800000 {
|
|
device_type = "pci";
|
|
compatible = "spacemit,k1-pcie";
|
|
reg = <0x0 0xca800000 0x0 0x00001000>,
|
|
<0x0 0xcab00000 0x0 0x0001ff24>,
|
|
<0x0 0xb7000000 0x0 0x00002000>,
|
|
<0x0 0xc0d20000 0x0 0x00001000>;
|
|
reg-names = "dbi",
|
|
"atu",
|
|
"config",
|
|
"link";
|
|
linux,pci-domain = <2>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
|
|
<0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
|
|
<0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
|
|
interrupts = <143>;
|
|
interrupt-names = "msi";
|
|
clocks = <&syscon_apmu CLK_PCIE2_DBI>,
|
|
<&syscon_apmu CLK_PCIE2_MASTER>,
|
|
<&syscon_apmu CLK_PCIE2_SLAVE>;
|
|
clock-names = "dbi",
|
|
"mstr",
|
|
"slv";
|
|
resets = <&syscon_apmu RESET_PCIE2_DBI>,
|
|
<&syscon_apmu RESET_PCIE2_MASTER>,
|
|
<&syscon_apmu RESET_PCIE2_SLAVE>;
|
|
reset-names = "dbi",
|
|
"mstr",
|
|
"slv";
|
|
spacemit,apmu = <&syscon_apmu 0x3dc>;
|
|
status = "disabled";
|
|
|
|
pcie2_port: pcie@0 {
|
|
device_type = "pci";
|
|
compatible = "pciclass,0604";
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
bus-range = <0x01 0xff>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
};
|
|
};
|
|
};
|
|
|
|
storage-bus {
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
|
|
|
|
usb_dwc3: usb@c0a00000 {
|
|
compatible = "spacemit,k1-dwc3";
|
|
reg = <0x0 0xc0a00000 0x0 0x10000>;
|
|
clocks = <&syscon_apmu CLK_USB30>;
|
|
clock-names = "usbdrd30";
|
|
interrupts = <125>;
|
|
phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
phy_type = "utmi";
|
|
resets = <&syscon_apmu RESET_USB30_AHB>,
|
|
<&syscon_apmu RESET_USB30_VCC>,
|
|
<&syscon_apmu RESET_USB30_PHY>;
|
|
reset-names = "ahb", "vcc", "phy";
|
|
reset-delay = <2>;
|
|
snps,hsphy_interface = "utmi";
|
|
snps,dis_enblslpm_quirk;
|
|
snps,dis-u2-freeclk-exists-quirk;
|
|
snps,dis-del-phy-power-chg-quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci0: mmc@d4280000 {
|
|
compatible = "spacemit,k1-sdhci";
|
|
reg = <0x0 0xd4280000 0x0 0x200>;
|
|
clocks = <&syscon_apmu CLK_SDH_AXI>,
|
|
<&syscon_apmu CLK_SDH0>;
|
|
clock-names = "core", "io";
|
|
resets = <&syscon_apmu RESET_SDH_AXI>,
|
|
<&syscon_apmu RESET_SDH0>;
|
|
reset-names = "axi", "sdh";
|
|
interrupts = <99>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: mmc@d4281000 {
|
|
compatible = "spacemit,k1-sdhci";
|
|
reg = <0x0 0xd4281000 0x0 0x200>;
|
|
clocks = <&syscon_apmu CLK_SDH_AXI>,
|
|
<&syscon_apmu CLK_SDH2>;
|
|
clock-names = "core", "io";
|
|
resets = <&syscon_apmu RESET_SDH_AXI>,
|
|
<&syscon_apmu RESET_SDH2>;
|
|
reset-names = "axi", "sdh";
|
|
interrupts = <101>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|