509 lines
22 KiB
C
509 lines
22 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G3L CPG driver
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*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
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#include "rzg2l-cpg.h"
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/* RZ/G3L Specific registers. */
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#define G3L_CPG_PL2_DDIV (0x204)
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#define G3L_CPG_PL3_DDIV (0x208)
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#define G3L_CPG_CA55CORE_DDIV (0x234)
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#define G3L_CPG_RSCI_DDIV (0x238)
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#define G3L_CPG_RSPI_DDIV (0x23c)
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#define G3L_CLKDIVSTATUS (0x280)
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#define G3L_CPG_ETH_SSEL (0x410)
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#define G3L_CPG_RSCI_SSEL (0x414)
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#define G3L_CPG_RSPI_SSEL (0x418)
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#define G3L_CPG_ETH_SDIV (0x434)
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/* RZ/G3L Specific division configuration. */
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#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
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#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
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#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
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#define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3)
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#define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3)
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#define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3)
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#define G3L_DIV_CA55_CORE3 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 12, 3)
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#define G3L_DIV_RSCI0 DDIV_PACK(G3L_CPG_RSCI_DDIV, 0, 2)
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#define G3L_DIV_RSCI1 DDIV_PACK(G3L_CPG_RSCI_DDIV, 2, 2)
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#define G3L_DIV_RSCI2 DDIV_PACK(G3L_CPG_RSCI_DDIV, 4, 2)
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#define G3L_DIV_RSCI3 DDIV_PACK(G3L_CPG_RSCI_DDIV, 6, 2)
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#define G3L_DIV_RSPI0 DDIV_PACK(G3L_CPG_RSPI_DDIV, 0, 2)
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#define G3L_DIV_RSPI1 DDIV_PACK(G3L_CPG_RSPI_DDIV, 2, 2)
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#define G3L_DIV_RSPI2 DDIV_PACK(G3L_CPG_RSPI_DDIV, 4, 2)
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#define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2)
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#define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1)
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#define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2)
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#define G3L_SDIV_ETH_D DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1)
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/* RZ/G3L Clock status configuration. */
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#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
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#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
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#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
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#define G3L_DIV_CA55_CORE0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 12, 1)
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#define G3L_DIV_CA55_CORE1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 13, 1)
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#define G3L_DIV_CA55_CORE2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 14, 1)
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#define G3L_DIV_CA55_CORE3_STS DDIV_PACK(G3L_CLKDIVSTATUS, 15, 1)
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#define G3L_DIV_RSCI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 16, 1)
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#define G3L_DIV_RSCI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 17, 1)
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#define G3L_DIV_RSCI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 18, 1)
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#define G3L_DIV_RSCI3_STS DDIV_PACK(G3L_CLKDIVSTATUS, 19, 1)
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#define G3L_DIV_RSPI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 20, 1)
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#define G3L_DIV_RSPI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 21, 1)
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#define G3L_DIV_RSPI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 22, 1)
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/* RZ/G3L Specific clocks select. */
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#define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1)
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#define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1)
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#define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1)
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#define G3L_SEL_ETH0_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 3, 1)
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#define G3L_SEL_ETH0_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 4, 1)
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#define G3L_SEL_ETH1_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 8, 1)
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#define G3L_SEL_ETH1_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 9, 1)
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#define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1)
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#define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1)
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#define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1)
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#define G3L_SEL_RSCI0 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 0, 2)
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#define G3L_SEL_RSCI1 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 2, 2)
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#define G3L_SEL_RSCI2 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 4, 2)
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#define G3L_SEL_RSCI3 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 6, 2)
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#define G3L_SEL_RSPI0 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 0, 2)
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#define G3L_SEL_RSPI1 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 2, 2)
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#define G3L_SEL_RSPI2 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 4, 2)
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_ETH0_TXC_TX_CLK_IN,
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CLK_ETH0_RXC_RX_CLK_IN,
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CLK_ETH1_TXC_TX_CLK_IN,
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CLK_ETH1_RXC_RX_CLK_IN,
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/* Internal Core Clocks */
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL2_DIV2,
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CLK_PLL2_DIV2_4,
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CLK_PLL2_DIV5,
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CLK_PLL2_DIV6,
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CLK_PLL2_DIV7,
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CLK_PLL3,
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CLK_PLL3_DIV2,
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CLK_PLL6,
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CLK_PLL6_DIV10,
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CLK_SEL_ETH0_TX,
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CLK_SEL_ETH0_RX,
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CLK_SEL_ETH0_RM,
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CLK_SEL_ETH1_TX,
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CLK_SEL_ETH1_RX,
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CLK_SEL_ETH1_RM,
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CLK_SEL_RSCI0,
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CLK_SEL_RSCI1,
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CLK_SEL_RSCI2,
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CLK_SEL_RSCI3,
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CLK_SEL_RSPI0,
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CLK_SEL_RSPI1,
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CLK_SEL_RSPI2,
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CLK_ETH0_TR,
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CLK_ETH0_RM,
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CLK_ETH1_TR,
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CLK_ETH1_RM,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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/* Divider tables */
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static const struct clk_div_table dtable_1_8[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_1_32[] = {
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{ 0, 1 },
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{ 1, 2 },
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{ 2, 4 },
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{ 3, 8 },
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{ 4, 16 },
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{ 5, 32 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_2_20[] = {
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{ 0, 2 },
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{ 1, 20 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_2_16[] = {
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{ 0, 2 },
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{ 1, 4 },
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{ 2, 8 },
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{ 3, 16 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_4_128[] = {
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{ 0, 4 },
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{ 1, 8 },
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{ 2, 16 },
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{ 3, 128 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_4_200[] = {
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{ 0, 4 },
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{ 1, 20 },
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{ 2, 200 },
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{ 0, 0 },
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};
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static const struct clk_div_table dtable_8_256[] = {
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{ 0, 8 },
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{ 1, 16 },
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{ 2, 32 },
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{ 3, 256 },
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{ 0, 0 },
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};
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/* Mux clock names tables. */
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static const char * const sel_eth0_tx[] = { ".div_eth0_tr", "eth0_txc_tx_clk" };
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static const char * const sel_eth0_rx[] = { ".div_eth0_tr", "eth0_rxc_rx_clk" };
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static const char * const sel_eth0_rm[] = { ".pll6_div10", "eth0_rxc_rx_clk" };
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static const char * const sel_eth1_tx[] = { ".div_eth1_tr", "eth1_txc_tx_clk" };
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static const char * const sel_eth1_rx[] = { ".div_eth1_tr", "eth1_rxc_rx_clk" };
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static const char * const sel_eth1_rm[] = { ".pll6_div10", "eth1_rxc_rx_clk" };
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static const char * const sel_rsci_rspi[] = { ".pll2_div5", ".pll2_div6", ".pll2_div7", ".pll2_div2_4" };
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static const char * const sel_eth0_clk_tx_i[] = { ".sel_eth0_tx", ".div_eth0_rm" };
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static const char * const sel_eth0_clk_rx_i[] = { ".sel_eth0_rx", ".div_eth0_rm" };
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static const char * const sel_eth1_clk_tx_i[] = { ".sel_eth1_tx", ".div_eth1_rm" };
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static const char * const sel_eth1_clk_rx_i[] = { ".sel_eth1_rx", ".div_eth1_rm" };
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static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN),
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DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN),
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DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN),
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DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
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/* Internal Core Clocks */
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DEF_G3L_PLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_PLL_CONF(0, 0x100),
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1200000000UL),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, CPG_PLL_CONF(0x50, 0),
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500000000UL),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".pll2_div2_4", CLK_PLL2_DIV2_4, CLK_PLL2_DIV2, 1, 4),
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DEF_FIXED(".pll2_div5", CLK_PLL2_DIV5, CLK_PLL2, 1, 5),
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DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6),
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DEF_FIXED(".pll2_div7", CLK_PLL2_DIV7, CLK_PLL2, 1, 7),
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DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
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DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10),
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DEF_MUX(".sel_rsci0", CLK_SEL_RSCI0, G3L_SEL_RSCI0, sel_rsci_rspi),
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DEF_MUX(".sel_rsci1", CLK_SEL_RSCI1, G3L_SEL_RSCI1, sel_rsci_rspi),
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DEF_MUX(".sel_rsci2", CLK_SEL_RSCI2, G3L_SEL_RSCI2, sel_rsci_rspi),
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DEF_MUX(".sel_rsci3", CLK_SEL_RSCI3, G3L_SEL_RSCI3, sel_rsci_rspi),
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DEF_MUX(".sel_rspi0", CLK_SEL_RSPI0, G3L_SEL_RSPI0, sel_rsci_rspi),
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DEF_MUX(".sel_rspi1", CLK_SEL_RSPI1, G3L_SEL_RSPI1, sel_rsci_rspi),
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DEF_MUX(".sel_rspi2", CLK_SEL_RSPI2, G3L_SEL_RSPI2, sel_rsci_rspi),
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DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx),
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DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx),
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DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm),
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DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx),
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DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx),
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DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm),
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DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_200),
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DEF_DIV(".div_eth1_tr", CLK_ETH1_TR, CLK_PLL6, G3L_SDIV_ETH_C, dtable_4_200),
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DEF_DIV(".div_eth0_rm", CLK_ETH0_RM, CLK_SEL_ETH0_RM, G3L_SDIV_ETH_B, dtable_2_20),
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DEF_DIV(".div_eth1_rm", CLK_ETH1_RM, CLK_SEL_ETH1_RM, G3L_SDIV_ETH_D, dtable_2_20),
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/* Core output clk */
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DEF_G3S_DIV("IC0", R9A08G046_CLK_IC0, CLK_PLL1, G3L_DIV_CA55_CORE0, G3L_DIV_CA55_CORE0_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("IC1", R9A08G046_CLK_IC1, CLK_PLL1, G3L_DIV_CA55_CORE1, G3L_DIV_CA55_CORE1_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("IC2", R9A08G046_CLK_IC2, CLK_PLL1, G3L_DIV_CA55_CORE2, G3L_DIV_CA55_CORE2_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("IC3", R9A08G046_CLK_IC3, CLK_PLL1, G3L_DIV_CA55_CORE3, G3L_DIV_CA55_CORE3_STS,
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dtable_1_32, 0, 0, 0, NULL),
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DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
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dtable_8_256, 0, 0, 0, NULL),
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DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
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dtable_4_128, 0, 0, 0, NULL),
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DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
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dtable_4_128, 0, 0, 0, NULL),
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DEF_G3S_DIV("P13", R9A08G046_CLK_P13, CLK_SEL_RSCI0, G3L_DIV_RSCI0, G3L_DIV_RSCI0_STS,
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dtable_2_16, 0, 100000000UL, 0, NULL),
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DEF_G3S_DIV("P14", R9A08G046_CLK_P14, CLK_SEL_RSCI1, G3L_DIV_RSCI1, G3L_DIV_RSCI1_STS,
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dtable_2_16, 0, 100000000UL, 0, NULL),
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DEF_G3S_DIV("P15", R9A08G046_CLK_P15, CLK_SEL_RSCI2, G3L_DIV_RSCI2, G3L_DIV_RSCI2_STS,
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dtable_2_16, 0, 100000000UL, 0, NULL),
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DEF_G3S_DIV("P16", R9A08G046_CLK_P16, CLK_SEL_RSCI3, G3L_DIV_RSCI3, G3L_DIV_RSCI3_STS,
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dtable_2_16, 0, 100000000UL, 0, NULL),
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DEF_G3S_DIV("P17", R9A08G046_CLK_P17, CLK_SEL_RSPI0, G3L_DIV_RSPI0, G3L_DIV_RSPI0_STS,
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dtable_1_8, 0, 200000000UL, 0, NULL),
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DEF_G3S_DIV("P18", R9A08G046_CLK_P18, CLK_SEL_RSPI1, G3L_DIV_RSPI1, G3L_DIV_RSPI1_STS,
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dtable_1_8, 0, 200000000UL, 0, NULL),
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DEF_G3S_DIV("P19", R9A08G046_CLK_P19, CLK_SEL_RSPI2, G3L_DIV_RSPI2, G3L_DIV_RSPI2_STS,
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dtable_1_8, 0, 200000000UL, 0, NULL),
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DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1),
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DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, sel_eth0_clk_tx_i,
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CLK_SET_RATE_PARENT),
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DEF_MUX_FLAGS("ETHRX01", R9A08G046_CLK_ETHRX01, G3L_SEL_ETH0_CLK_RX_I, sel_eth0_clk_rx_i,
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CLK_SET_RATE_PARENT),
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DEF_MUX_FLAGS("ETHTX11", R9A08G046_CLK_ETHTX11, G3L_SEL_ETH1_CLK_TX_I, sel_eth1_clk_tx_i,
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CLK_SET_RATE_PARENT),
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DEF_MUX_FLAGS("ETHRX11", R9A08G046_CLK_ETHRX11, G3L_SEL_ETH1_CLK_RX_I, sel_eth1_clk_rx_i,
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CLK_SET_RATE_PARENT),
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DEF_FIXED("ETHRM0", R9A08G046_CLK_ETHRM0, CLK_SEL_ETH0_RM, 1, 1),
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DEF_FIXED("ETHTX02", R9A08G046_CLK_ETHTX02, CLK_SEL_ETH0_TX, 1, 1),
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DEF_FIXED("ETHRX02", R9A08G046_CLK_ETHRX02, CLK_SEL_ETH0_RX, 1, 1),
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DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_SEL_ETH1_RM, 1, 1),
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DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1),
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DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1),
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DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1),
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};
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static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
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DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, 0,
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MSTOP(BUS_PERI_COM, BIT(12))),
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DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0,
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MSTOP(BUS_PERI_CPU, BIT(13))),
|
|
DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1,
|
|
MSTOP(BUS_PERI_CPU, BIT(13))),
|
|
DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0,
|
|
MSTOP(BUS_REG1, BIT(2))),
|
|
DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
|
|
MSTOP(BUS_REG1, BIT(3))),
|
|
DEF_MOD("wdt0_pclk", R9A08G046_WDT0_PCLK, R9A08G046_CLK_P0, 0x548, 0,
|
|
MSTOP(BUS_REG0, BIT(0))),
|
|
DEF_MOD("wdt0_clk", R9A08G046_WDT0_CLK, R9A08G046_OSCCLK, 0x548, 1,
|
|
MSTOP(BUS_REG0, BIT(0))),
|
|
DEF_MOD("ssi0_pclk2", R9A08G046_SSI0_PCLK2, R9A08G046_CLK_P0, 0x570, 0,
|
|
MSTOP(BUS_MCPU1, BIT(10))),
|
|
DEF_MOD("ssi0_pclk_sfr", R9A08G046_SSI0_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 1,
|
|
MSTOP(BUS_MCPU1, BIT(10))),
|
|
DEF_MOD("ssi1_pclk2", R9A08G046_SSI1_PCLK2, R9A08G046_CLK_P0, 0x570, 2,
|
|
MSTOP(BUS_MCPU1, BIT(11))),
|
|
DEF_MOD("ssi1_pclk_sfr", R9A08G046_SSI1_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 3,
|
|
MSTOP(BUS_MCPU1, BIT(11))),
|
|
DEF_MOD("ssi2_pclk2", R9A08G046_SSI2_PCLK2, R9A08G046_CLK_P0, 0x570, 4,
|
|
MSTOP(BUS_MCPU1, BIT(12))),
|
|
DEF_MOD("ssi2_pclk_sfr", R9A08G046_SSI2_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 5,
|
|
MSTOP(BUS_MCPU1, BIT(12))),
|
|
DEF_MOD("ssi3_pclk2", R9A08G046_SSI3_PCLK2, R9A08G046_CLK_P0, 0x570, 6,
|
|
MSTOP(BUS_MCPU1, BIT(13))),
|
|
DEF_MOD("ssi3_pclk_sfr", R9A08G046_SSI3_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 7,
|
|
MSTOP(BUS_MCPU1, BIT(13))),
|
|
DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 0,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 1,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_MOD("eth0_clk_chi", R9A08G046_ETH0_CLK_CHI, R9A08G046_CLK_P1, 0x57c, 2,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_MOD("eth1_clk_chi", R9A08G046_ETH1_CLK_CHI, R9A08G046_CLK_P1, 0x57c, 3,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_COUPLED("eth0_tx_i", R9A08G046_ETH0_CLK_TX_I, R9A08G046_CLK_ETHTX01, 0x57c, 4,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_COUPLED("eth0_tx_180_i", R9A08G046_ETH0_CLK_TX_180_I, R9A08G046_CLK_ETHTX02, 0x57c, 4,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_COUPLED("eth1_tx_i", R9A08G046_ETH1_CLK_TX_I, R9A08G046_CLK_ETHTX11, 0x57c, 5,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_COUPLED("eth1_tx_180_i", R9A08G046_ETH1_CLK_TX_180_I, R9A08G046_CLK_ETHTX12, 0x57c, 5,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_COUPLED("eth0_rx_i", R9A08G046_ETH0_CLK_RX_I, R9A08G046_CLK_ETHRX01, 0x57c, 6,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_COUPLED("eth0_rx_180_i", R9A08G046_ETH0_CLK_RX_180_I, R9A08G046_CLK_ETHRX02, 0x57c, 6,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_COUPLED("eth1_rx_i", R9A08G046_ETH1_CLK_RX_I, R9A08G046_CLK_ETHRX11, 0x57c, 7,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_COUPLED("eth1_rx_180_i", R9A08G046_ETH1_CLK_RX_180_I, R9A08G046_CLK_ETHRX12, 0x57c, 7,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_MOD("eth0_ptp_ref_i", R9A08G046_ETH0_CLK_PTP_REF_I, R9A08G046_CLK_HP, 0x57c, 8,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_MOD("eth1_ptp_ref_i", R9A08G046_ETH1_CLK_PTP_REF_I, R9A08G046_CLK_HP, 0x57c, 9,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_MOD("eth0_rmii_i", R9A08G046_ETH0_CLK_RMII_I, R9A08G046_CLK_ETHRM0, 0x57c, 10,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_MOD("eth1_rmii_i", R9A08G046_ETH1_CLK_RMII_I, R9A08G046_CLK_ETHRM1, 0x57c, 11,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_COUPLED("eth0_tx_i_rmii", R9A08G046_ETH0_CLK_TX_I_RMII, R9A08G046_CLK_ETHTX01, 0x57c, 12,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_COUPLED("eth0_rx_i_rmii", R9A08G046_ETH0_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX01, 0x57c, 12,
|
|
MSTOP(BUS_PERI_COM, BIT(2))),
|
|
DEF_COUPLED("eth1_tx_i_rmii", R9A08G046_ETH1_CLK_TX_I_RMII, R9A08G046_CLK_ETHTX11, 0x57c, 13,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_COUPLED("eth1_rx_i_rmii", R9A08G046_ETH1_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX11, 0x57c, 13,
|
|
MSTOP(BUS_PERI_COM, BIT(3))),
|
|
DEF_MOD("i2c0_pclk", R9A08G046_I2C0_PCLK, R9A08G046_CLK_P0, 0x580, 0,
|
|
MSTOP(BUS_MCPU2, BIT(10))),
|
|
DEF_MOD("i2c1_pclk", R9A08G046_I2C1_PCLK, R9A08G046_CLK_P0, 0x580, 1,
|
|
MSTOP(BUS_MCPU2, BIT(11))),
|
|
DEF_MOD("i2c2_pclk", R9A08G046_I2C2_PCLK, R9A08G046_CLK_P0, 0x580, 2,
|
|
MSTOP(BUS_MCPU2, BIT(12))),
|
|
DEF_MOD("i2c3_pclk", R9A08G046_I2C3_PCLK, R9A08G046_CLK_P0, 0x580, 3,
|
|
MSTOP(BUS_MCPU2, BIT(13))),
|
|
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
|
|
MSTOP(BUS_MCPU2, BIT(1))),
|
|
DEF_MOD("scif1_clk_pck", R9A08G046_SCIF1_CLK_PCK, R9A08G046_CLK_P0, 0x584, 1,
|
|
MSTOP(BUS_MCPU2, BIT(2))),
|
|
DEF_MOD("scif2_clk_pck", R9A08G046_SCIF2_CLK_PCK, R9A08G046_CLK_P0, 0x584, 2,
|
|
MSTOP(BUS_MCPU2, BIT(3))),
|
|
DEF_MOD("scif3_clk_pck", R9A08G046_SCIF3_CLK_PCK, R9A08G046_CLK_P0, 0x584, 3,
|
|
MSTOP(BUS_MCPU2, BIT(4))),
|
|
DEF_MOD("scif4_clk_pck", R9A08G046_SCIF4_CLK_PCK, R9A08G046_CLK_P0, 0x584, 4,
|
|
MSTOP(BUS_MCPU2, BIT(5))),
|
|
DEF_MOD("scif5_clk_pck", R9A08G046_SCIF5_CLK_PCK, R9A08G046_CLK_P0, 0x584, 5,
|
|
MSTOP(BUS_MCPU3, BIT(4))),
|
|
DEF_MOD("rspi0_pclk", R9A08G046_RSPI0_PCLK, R9A08G046_CLK_P3, 0x590, 0,
|
|
MSTOP(BUS_MCPU1, BIT(14))),
|
|
DEF_MOD("rspi1_pclk", R9A08G046_RSPI1_PCLK, R9A08G046_CLK_P3, 0x590, 1,
|
|
MSTOP(BUS_MCPU1, BIT(15))),
|
|
DEF_MOD("rspi2_pclk", R9A08G046_RSPI2_PCLK, R9A08G046_CLK_P3, 0x590, 2,
|
|
MSTOP(BUS_MCPU2, BIT(0))),
|
|
DEF_MOD("rspi0_tclk", R9A08G046_RSPI0_TCLK, R9A08G046_CLK_P17, 0x590, 8,
|
|
MSTOP(BUS_MCPU1, BIT(14))),
|
|
DEF_MOD("rspi1_tclk", R9A08G046_RSPI1_TCLK, R9A08G046_CLK_P18, 0x590, 9,
|
|
MSTOP(BUS_MCPU1, BIT(15))),
|
|
DEF_MOD("rspi2_tclk", R9A08G046_RSPI2_TCLK, R9A08G046_CLK_P19, 0x590, 10,
|
|
MSTOP(BUS_MCPU2, BIT(0))),
|
|
DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
|
|
MSTOP(BUS_PERI_CPU, BIT(6))),
|
|
DEF_MOD("rsci0_pclk", R9A08G046_RSCI0_PCLK, R9A08G046_CLK_P0, 0x618, 0,
|
|
MSTOP(BUS_MCPU2, BIT(7))),
|
|
DEF_MOD("rsci1_pclk", R9A08G046_RSCI1_PCLK, R9A08G046_CLK_P0, 0x618, 1,
|
|
MSTOP(BUS_MCPU2, BIT(8))),
|
|
DEF_MOD("rsci2_pclk", R9A08G046_RSCI2_PCLK, R9A08G046_CLK_P0, 0x618, 2,
|
|
MSTOP(BUS_MCPU3, BIT(11))),
|
|
DEF_MOD("rsci3_pclk", R9A08G046_RSCI3_PCLK, R9A08G046_CLK_P0, 0x618, 3,
|
|
MSTOP(BUS_MCPU3, BIT(12))),
|
|
DEF_MOD("rsci0_tclk", R9A08G046_RSCI0_TCLK, R9A08G046_CLK_P13, 0x618, 8,
|
|
MSTOP(BUS_MCPU2, BIT(7))),
|
|
DEF_MOD("rsci1_tclk", R9A08G046_RSCI1_TCLK, R9A08G046_CLK_P14, 0x618, 9,
|
|
MSTOP(BUS_MCPU2, BIT(8))),
|
|
DEF_MOD("rsci2_tclk", R9A08G046_RSCI2_TCLK, R9A08G046_CLK_P15, 0x618, 10,
|
|
MSTOP(BUS_MCPU3, BIT(11))),
|
|
DEF_MOD("rsci3_tclk", R9A08G046_RSCI3_TCLK, R9A08G046_CLK_P16, 0x618, 11,
|
|
MSTOP(BUS_MCPU3, BIT(12))),
|
|
};
|
|
|
|
static const struct rzg2l_reset r9a08g046_resets[] = {
|
|
DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0),
|
|
DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1),
|
|
DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
|
|
DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
|
|
DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
|
|
DEF_RST(R9A08G046_WDT0_PRESETN, 0x848, 0),
|
|
DEF_RST(R9A08G046_SSI0_RST_M2_REG, 0x870, 0),
|
|
DEF_RST(R9A08G046_SSI1_RST_M2_REG, 0x870, 1),
|
|
DEF_RST(R9A08G046_SSI2_RST_M2_REG, 0x870, 2),
|
|
DEF_RST(R9A08G046_SSI3_RST_M2_REG, 0x870, 3),
|
|
DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
|
|
DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
|
|
DEF_RST(R9A08G046_I2C0_MRST, 0x880, 0),
|
|
DEF_RST(R9A08G046_I2C1_MRST, 0x880, 1),
|
|
DEF_RST(R9A08G046_I2C2_MRST, 0x880, 2),
|
|
DEF_RST(R9A08G046_I2C3_MRST, 0x880, 3),
|
|
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
|
|
DEF_RST(R9A08G046_SCIF1_RST_SYSTEM_N, 0x884, 1),
|
|
DEF_RST(R9A08G046_SCIF2_RST_SYSTEM_N, 0x884, 2),
|
|
DEF_RST(R9A08G046_SCIF3_RST_SYSTEM_N, 0x884, 3),
|
|
DEF_RST(R9A08G046_SCIF4_RST_SYSTEM_N, 0x884, 4),
|
|
DEF_RST(R9A08G046_SCIF5_RST_SYSTEM_N, 0x884, 5),
|
|
DEF_RST(R9A08G046_RSPI0_PRESETN, 0x890, 0),
|
|
DEF_RST(R9A08G046_RSPI1_PRESETN, 0x890, 1),
|
|
DEF_RST(R9A08G046_RSPI2_PRESETN, 0x890, 2),
|
|
DEF_RST(R9A08G046_RSPI0_TRESETN, 0x890, 8),
|
|
DEF_RST(R9A08G046_RSPI1_TRESETN, 0x890, 9),
|
|
DEF_RST(R9A08G046_RSPI2_TRESETN, 0x890, 10),
|
|
DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
|
|
DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
|
|
DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),
|
|
DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0),
|
|
DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1),
|
|
DEF_RST(R9A08G046_RSCI2_PRESETN, 0x918, 2),
|
|
DEF_RST(R9A08G046_RSCI3_PRESETN, 0x918, 3),
|
|
DEF_RST(R9A08G046_RSCI0_TRESETN, 0x918, 8),
|
|
DEF_RST(R9A08G046_RSCI1_TRESETN, 0x918, 9),
|
|
DEF_RST(R9A08G046_RSCI2_TRESETN, 0x918, 10),
|
|
DEF_RST(R9A08G046_RSCI3_TRESETN, 0x918, 11),
|
|
};
|
|
|
|
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
|
|
MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
|
|
MOD_CLK_BASE + R9A08G046_IA55_PCLK,
|
|
MOD_CLK_BASE + R9A08G046_IA55_CLK,
|
|
MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
|
|
};
|
|
|
|
static const unsigned int r9a08g046_crit_resets[] = {
|
|
R9A08G046_DMAC_ARESETN,
|
|
R9A08G046_DMAC_RST_ASYNC,
|
|
};
|
|
|
|
static const unsigned int r9a08g046_no_pm_mod_clks[] = {
|
|
MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_180_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_180_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RMII_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_I_RMII,
|
|
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_I_RMII,
|
|
MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_180_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_180_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RMII_I,
|
|
MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I_RMII,
|
|
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I_RMII,
|
|
};
|
|
|
|
const struct rzg2l_cpg_info r9a08g046_cpg_info = {
|
|
/* Core Clocks */
|
|
.core_clks = r9a08g046_core_clks,
|
|
.num_core_clks = ARRAY_SIZE(r9a08g046_core_clks),
|
|
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
|
.num_total_core_clks = MOD_CLK_BASE,
|
|
|
|
/* Critical Module Clocks */
|
|
.crit_mod_clks = r9a08g046_crit_mod_clks,
|
|
.num_crit_mod_clks = ARRAY_SIZE(r9a08g046_crit_mod_clks),
|
|
|
|
/* Module Clocks */
|
|
.mod_clks = r9a08g046_mod_clks,
|
|
.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
|
|
.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
|
|
|
|
/* No PM modules Clocks */
|
|
.no_pm_mod_clks = r9a08g046_no_pm_mod_clks,
|
|
.num_no_pm_mod_clks = ARRAY_SIZE(r9a08g046_no_pm_mod_clks),
|
|
|
|
/* Resets */
|
|
.resets = r9a08g046_resets,
|
|
.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */
|
|
|
|
/* Critical Resets */
|
|
.crit_resets = r9a08g046_crit_resets,
|
|
.num_crit_resets = ARRAY_SIZE(r9a08g046_crit_resets),
|
|
|
|
.has_clk_mon_regs = true,
|
|
};
|