264 lines
7.9 KiB
C
264 lines
7.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Copyright (c) 2021 BayLibre, SAS
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* Copyright (c) 2024 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#ifndef _MTK_HDMI_REGS_H
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#define _MTK_HDMI_REGS_H
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/* HDMI_TOP Config */
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#define TOP_CFG00 0x000
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#define HDMI2_ON BIT(2)
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#define HDMI_MODE_HDMI BIT(3)
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#define SCR_ON BIT(4)
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#define TMDS_PACK_MODE GENMASK(9, 8)
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#define TMDS_PACK_MODE_8BPP 0
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#define TMDS_PACK_MODE_10BPP 1
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#define TMDS_PACK_MODE_12BPP 2
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#define TMDS_PACK_MODE_16BPP 3
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#define DEEPCOLOR_PKT_EN BIT(12)
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#define HDMI_ABIST_VIDEO_FORMAT GENMASK(21, 16)
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#define HDMI_ABIST_ENABLE BIT(31)
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#define TOP_CFG01 0x004
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#define CP_SET_MUTE_EN BIT(0)
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#define CP_CLR_MUTE_EN BIT(1)
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#define NULL_PKT_EN BIT(2)
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#define NULL_PKT_VSYNC_HIGH_EN BIT(3)
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/* HDMI_TOP Audio: Channel Mapping */
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#define TOP_AUD_MAP 0x00c
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#define SD0_MAP GENMASK(2, 0)
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#define SD1_MAP GENMASK(6, 4)
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#define SD2_MAP GENMASK(10, 8)
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#define SD3_MAP GENMASK(14, 12)
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#define SD4_MAP GENMASK(18, 16)
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#define SD5_MAP GENMASK(22, 20)
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#define SD6_MAP GENMASK(26, 24)
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#define SD7_MAP GENMASK(30, 28)
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/* Auxiliary Video Information (AVI) Infoframe */
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#define TOP_AVI_HEADER 0x024
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#define TOP_AVI_PKT00 0x028
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#define TOP_AVI_PKT01 0x02C
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#define TOP_AVI_PKT02 0x030
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#define TOP_AVI_PKT03 0x034
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#define TOP_AVI_PKT04 0x038
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#define TOP_AVI_PKT05 0x03C
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/* Audio Interface Infoframe */
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#define TOP_AIF_HEADER 0x040
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#define TOP_AIF_PKT00 0x044
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#define TOP_AIF_PKT01 0x048
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#define TOP_AIF_PKT02 0x04c
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#define TOP_AIF_PKT03 0x050
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/* Audio SPDIF Infoframe */
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#define TOP_SPDIF_HEADER 0x054
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#define TOP_SPDIF_PKT00 0x058
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#define TOP_SPDIF_PKT01 0x05c
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#define TOP_SPDIF_PKT02 0x060
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#define TOP_SPDIF_PKT03 0x064
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#define TOP_SPDIF_PKT04 0x068
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#define TOP_SPDIF_PKT05 0x06c
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#define TOP_SPDIF_PKT06 0x070
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#define TOP_SPDIF_PKT07 0x074
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/* Infoframes Configuration */
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#define TOP_INFO_EN 0x01c
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#define AVI_EN BIT(0)
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#define SPD_EN BIT(1)
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#define AUD_EN BIT(2)
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#define CP_EN BIT(5)
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#define VSIF_EN BIT(11)
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#define AVI_EN_WR BIT(16)
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#define SPD_EN_WR BIT(17)
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#define AUD_EN_WR BIT(18)
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#define CP_EN_WR BIT(21)
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#define VSIF_EN_WR BIT(27)
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#define TOP_INFO_RPT 0x020
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#define AVI_RPT_EN BIT(0)
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#define SPD_RPT_EN BIT(1)
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#define AUD_RPT_EN BIT(2)
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#define CP_RPT_EN BIT(5)
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#define VSIF_RPT_EN BIT(11)
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/* Vendor Specific Infoframe */
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#define TOP_VSIF_HEADER 0x174
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#define TOP_VSIF_PKT00 0x178
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#define TOP_VSIF_PKT01 0x17c
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#define TOP_VSIF_PKT02 0x180
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#define TOP_VSIF_PKT03 0x184
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#define TOP_VSIF_PKT04 0x188
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#define TOP_VSIF_PKT05 0x18c
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#define TOP_VSIF_PKT06 0x190
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#define TOP_VSIF_PKT07 0x194
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/* HDMI_TOP Misc */
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#define TOP_MISC_CTLR 0x1a4
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#define DEEP_COLOR_ADD BIT(4)
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/* Hardware interrupts */
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#define TOP_INT_STA00 0x1a8
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#define TOP_INT_ENABLE00 0x1b0
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#define HTPLG_R_INT BIT(0)
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#define HTPLG_F_INT BIT(1)
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#define PORD_R_INT BIT(2)
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#define PORD_F_INT BIT(3)
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#define HDMI_VSYNC_INT BIT(4)
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#define HDMI_AUDIO_INT BIT(5)
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#define HDCP2X_RX_REAUTH_REQ_DDCM_INT BIT(25)
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#define TOP_INT_ENABLE01 0x1b4
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#define TOP_INT_CLR00 0x1b8
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#define TOP_INT_CLR01 0x1bc
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/* Video Mute */
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#define TOP_VMUTE_CFG1 0x1c8
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#define REG_VMUTE_EN BIT(16)
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/* HDMI Audio IP */
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#define AIP_CTRL 0x400
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#define CTS_SW_SEL BIT(0)
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#define CTS_REQ_EN BIT(1)
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#define MCLK_EN BIT(2)
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#define NO_MCLK_CTSGEN_SEL BIT(3)
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#define AUD_IN_EN BIT(8)
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#define AUD_SEL_OWRT BIT(9)
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#define SPDIF_EN BIT(13)
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#define HBRA_ON BIT(14)
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#define DSD_EN BIT(15)
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#define I2S_EN GENMASK(19, 16)
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#define HBR_FROM_SPDIF BIT(20)
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#define CTS_CAL_N4 BIT(23)
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#define SPDIF_INTERNAL_MODULE BIT(24)
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#define AIP_N_VAL 0x404
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#define AIP_CTS_SVAL 0x408
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#define AIP_SPDIF_CTRL 0x40c
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#define WR_1UI_LOCK BIT(0)
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#define FS_OVERRIDE_WRITE BIT(1)
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#define WR_2UI_LOCK BIT(2)
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#define MAX_1UI_WRITE GENMASK(15, 8)
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#define MAX_2UI_SPDIF_WRITE GENMASK(23, 16)
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#define MAX_2UI_I2S_HI_WRITE GENMASK(23, 20)
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#define MAX_2UI_I2S_LFE_CC_SWAP BIT(1)
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#define MAX_2UI_I2S_LO_WRITE GENMASK(19, 16)
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#define AUD_ERR_THRESH GENMASK(29, 24)
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#define I2S2DSD_EN BIT(30)
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#define AIP_I2S_CTRL 0x410
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#define FIFO0_MAP GENMASK(1, 0)
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#define FIFO1_MAP GENMASK(3, 2)
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#define FIFO2_MAP GENMASK(5, 4)
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#define FIFO3_MAP GENMASK(7, 6)
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#define I2S_1ST_BIT_NOSHIFT BIT(8)
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#define I2S_DATA_DIR_LSB BIT(9)
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#define JUSTIFY_RIGHT BIT(10)
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#define WS_HIGH BIT(11)
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#define VBIT_COMPRESSED BIT(12)
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#define CBIT_ORDER_SAME BIT(13)
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#define SCK_EDGE_RISE BIT(14)
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#define AIP_I2S_CHST0 0x414
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#define AIP_I2S_CHST1 0x418
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#define AIP_TXCTRL 0x424
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#define RST4AUDIO BIT(0)
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#define RST4AUDIO_FIFO BIT(1)
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#define RST4AUDIO_ACR BIT(2)
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#define AUD_LAYOUT_1 BIT(4)
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#define AUD_MUTE_FIFO_EN BIT(5)
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#define AUD_PACKET_DROP BIT(6)
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#define DSD_MUTE_EN BIT(7)
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#define AIP_TPI_CTRL 0x428
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#define TPI_AUDIO_LOOKUP_EN BIT(2)
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/* Video downsampling configuration */
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#define VID_DOWNSAMPLE_CONFIG 0x8d0
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#define C444_C422_CONFIG_ENABLE BIT(0)
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#define C422_C420_CONFIG_ENABLE BIT(4)
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#define C422_C420_CONFIG_BYPASS BIT(5)
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#define C422_C420_CONFIG_OUT_CB_OR_CR BIT(6)
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#define VID_OUT_FORMAT 0x8fc
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#define OUTPUT_FORMAT_DEMUX_420_ENABLE BIT(10)
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/* HDCP registers */
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#define HDCP_TOP_CTRL 0xc00
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#define HDCP2X_CTRL_0 0xc20
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#define HDCP2X_EN BIT(0)
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#define HDCP2X_ENCRYPT_EN BIT(7)
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#define HDCP2X_HPD_OVR BIT(10)
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#define HDCP2X_HPD_SW BIT(11)
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#define HDCP2X_POL_CTRL 0xc54
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#define HDCP2X_DIS_POLL_EN BIT(16)
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#define HDCP1X_CTRL 0xcd0
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#define HDCP1X_ENC_EN BIT(6)
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/* HDMI DDC registers */
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#define HPD_DDC_CTRL 0xc08
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#define HPD_DDC_DELAY_CNT GENMASK(31, 16)
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#define HPD_DDC_HPD_DBNC_EN BIT(2)
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#define HPD_DDC_PORD_DBNC_EN BIT(3)
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#define DDC_CTRL 0xc10
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#define DDC_CTRL_ADDR GENMASK(7, 1)
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#define DDC_CTRL_OFFSET GENMASK(15, 8)
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#define DDC_CTRL_DIN_CNT GENMASK(25, 16)
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#define DDC_CTRL_CMD GENMASK(31, 28)
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#define SCDC_CTRL 0xc18
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#define SCDC_DDC_SEGMENT GENMASK(15, 8)
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#define HPD_DDC_STATUS 0xc60
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#define HPD_STATE GENMASK(1, 0)
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#define HPD_STATE_CONNECTED 2
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#define HPD_PIN_STA BIT(4)
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#define PORD_PIN_STA BIT(5)
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#define DDC_I2C_IN_PROG BIT(13)
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#define DDC_DATA_OUT GENMASK(23, 16)
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#define SI2C_CTRL 0xcac
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#define SI2C_WR BIT(0)
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#define SI2C_RD BIT(1)
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#define SI2C_CONFIRM_READ BIT(2)
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#define SI2C_WDATA GENMASK(15, 8)
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#define SI2C_ADDR GENMASK(23, 16)
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/* HDCP DDC registers */
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#define HDCP2X_DDCM_STATUS 0xc68
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#define DDC_I2C_NO_ACK BIT(10)
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#define DDC_I2C_BUS_LOW BIT(11)
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/* HDMI TX registers */
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#define HDMITX_CONFIG_MT8188 0xea0
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#define HDMITX_CONFIG_MT8195 0x900
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#define HDMI_YUV420_MODE BIT(10)
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#define HDMITX_SW_HPD BIT(29)
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#define HDMITX_SW_RSTB BIT(31)
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/**
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* enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands
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* @DDC_CMD_READ_NOACK: Current address read with no ACK on last byte
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* @DDC_CMD_READ: Current address read with ACK on last byte
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* @DDC_CMD_SEQ_READ_NOACK: Sequential read with no ACK on last byte
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* @DDC_CMD_SEQ_READ: Sequential read with ACK on last byte
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* @DDC_CMD_ENH_READ_NOACK: Enhanced read with no ACK on last byte
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* @DDC_CMD_ENH_READ: Enhanced read with ACK on last byte
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* @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte
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* @DDC_CMD_SEQ_WRITE: Sequential write requiring ACK on last byte
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* @DDC_CMD_RSVD: Reserved for future use
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* @DDC_CMD_CLEAR_FIFO: Clear DDC I2C FIFO
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* @DDC_CMD_CLOCK_SCL: Start clocking DDC I2C SCL
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* @DDC_CMD_ABORT_XFER: Abort DDC I2C transaction
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*/
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enum mtk_hdmi_ddc_v2_cmds {
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DDC_CMD_READ_NOACK = 0x0,
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DDC_CMD_READ,
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DDC_CMD_SEQ_READ_NOACK,
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DDC_CMD_SEQ_READ,
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DDC_CMD_ENH_READ_NOACK,
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DDC_CMD_ENH_READ,
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DDC_CMD_SEQ_WRITE_NOACK,
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DDC_CMD_SEQ_WRITE = 0x07,
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DDC_CMD_CLEAR_FIFO = 0x09,
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DDC_CMD_CLOCK_SCL = 0x0a,
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DDC_CMD_ABORT_XFER = 0x0f
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};
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#endif /* _MTK_HDMI_REGS_H */
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