34 lines
1.1 KiB
C
34 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#ifndef _XE_PCODE_REGS_H_
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#define _XE_PCODE_REGS_H_
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#include "regs/xe_reg_defs.h"
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/*
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* This file contains addresses of PCODE registers visible through GT MMIO space.
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*/
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#define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
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#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
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#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
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#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
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#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
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#define BMG_FAN_1_SPEED XE_REG(0x138140)
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#define BMG_FAN_2_SPEED XE_REG(0x138170)
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#define BMG_FAN_3_SPEED XE_REG(0x1381a0)
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#define BMG_VRAM_TEMPERATURE_N(n) XE_REG(0x138260 + ((n) * (sizeof(u32))))
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#define BMG_VRAM_TEMPERATURE XE_REG(0x1382c0)
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#define TEMP_MASK_VRAM_N REG_GENMASK(30, 8)
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#define TEMP_SIGN_MASK REG_BIT(31)
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#define BMG_PACKAGE_TEMPERATURE XE_REG(0x138434)
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#define CRI_PACKAGE_ENERGY_STATUS XE_REG(0x138120)
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#define CRI_PLATFORM_ENERGY_STATUS XE_REG(0x138458)
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#endif /* _XE_PCODE_REGS_H_ */
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