112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023,2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _CORESIGHT_CORESIGHT_TPDA_H
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#define _CORESIGHT_CORESIGHT_TPDA_H
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#define TPDA_CR (0x000)
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#define TPDA_Pn_CR(n) (0x004 + (n * 4))
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#define TPDA_FPID_CR (0x084)
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#define TPDA_SYNCR (0x08C)
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#define TPDA_FLUSH_CR (0x090)
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/* Cross trigger global (all ports) flush request bit */
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#define TPDA_CR_FLREQ BIT(0)
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/* Cross trigger FREQ packets timestamp bit */
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#define TPDA_CR_FREQTS BIT(2)
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/* Cross trigger FREQ packet request bit */
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#define TPDA_CR_FRIE BIT(3)
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/* Cross trigger FLAG packet request interface bit */
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#define TPDA_CR_FLRIE BIT(4)
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/* Cross trigger synchronization bit */
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#define TPDA_CR_SRIE BIT(5)
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/* Bits 6 ~ 12 is for atid value */
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#define TPDA_CR_ATID GENMASK(12, 6)
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/*
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* Channel mode bit of the packetization of CMB/MCB traffic
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* 0 - raw channel mapping mode
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* 1 - channel pair marking mode
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*/
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#define TPDA_CR_CMBCHANMODE BIT(20)
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/* Aggregator port enable bit */
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#define TPDA_Pn_CR_ENA BIT(0)
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/* Aggregator port CMB data set element size bit */
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#define TPDA_Pn_CR_CMBSIZE GENMASK(7, 6)
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/* Aggregator port DSB data set element size bit */
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#define TPDA_Pn_CR_DSBSIZE BIT(8)
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/* TPDA_SYNCR count mask */
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#define TPDA_SYNCR_COUNT_MASK GENMASK(11, 0)
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/* TPDA_SYNCR mode control bit */
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#define TPDA_SYNCR_MODE_CTRL_MASK GENMASK(12, 12)
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#define TPDA_MAX_INPORTS 32
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/**
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* struct tpda_drvdata - specifics associated to an TPDA component
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* @base: memory mapped base address for this component.
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* @dev: The device entity associated to this component.
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* @csdev: component vitals needed by the framework.
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* @spinlock: lock for the drvdata value.
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* @enable: enable status of the component.
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* @dsb_esize Record the DSB element size.
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* @cmb_esize Record the CMB element size.
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* @trig_async: Enable/disable cross trigger synchronization sequence interface.
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* @trig_flag_ts: Enable/disable cross trigger FLAG packet request interface.
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* @trig_freq: Enable/disable cross trigger FREQ packet request interface.
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* @freq_ts: Enable/disable the timestamp for all FREQ packets.
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* @cmbchan_mode: Configure the CMB/MCMB channel mode.
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* @syncr_mode: Setting the mode for counting packets.
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* @syncr_count: Setting the value of the count.
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*/
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struct tpda_drvdata {
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void __iomem *base;
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struct device *dev;
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struct coresight_device *csdev;
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spinlock_t spinlock;
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u8 atid;
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u32 dsb_esize;
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u32 cmb_esize;
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bool trig_async;
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bool trig_flag_ts;
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bool trig_freq;
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bool freq_ts;
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bool cmbchan_mode;
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bool syncr_mode;
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u32 syncr_count;
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};
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/* Enumerate members of global control register(cr) */
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enum tpda_cr_mem {
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FREQTS,
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FRIE,
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FLRIE,
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SRIE,
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CMBCHANMODE
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};
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/**
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* struct tpda_trig_sysfs_attribute - Record the member variables of cross
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* trigger register that need to be operated by sysfs file
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* @attr: The device attribute
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* @mem: The member in the control register data structure
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*/
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struct tpda_trig_sysfs_attribute {
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struct device_attribute attr;
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enum tpda_cr_mem mem;
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};
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#define tpda_trig_sysfs_rw(name, mem) \
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(&((struct tpda_trig_sysfs_attribute[]) { \
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{ \
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__ATTR(name, 0644, tpda_trig_sysfs_show, \
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tpda_trig_sysfs_store), \
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mem, \
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} \
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})[0].attr.attr)
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#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
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