255 lines
6.9 KiB
C
255 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive JHB100 External Interrupt Controller driver
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*
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* Copyright (C) 2023 StarFive Technology Co., Ltd.
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*
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* Author: Changhuang Liang <changhuang.liang@starfivetech.com>
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*/
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#include <linux/bitops.h>
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#include <linux/cleanup.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#define STARFIVE_INTC_SRC_TYPE(n) (0x04 + ((n) * 0x20))
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#define STARFIVE_INTC_SRC_CLEAR(n) (0x10 + ((n) * 0x20))
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#define STARFIVE_INTC_SRC_MASK(n) (0x14 + ((n) * 0x20))
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#define STARFIVE_INTC_SRC_INT(n) (0x1c + ((n) * 0x20))
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#define STARFIVE_INTC_TRIGGER_MASK 0x3
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#define STARFIVE_INTC_TRIGGER_HIGH 0
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#define STARFIVE_INTC_TRIGGER_LOW 1
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#define STARFIVE_INTC_TRIGGER_POSEDGE 2
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#define STARFIVE_INTC_TRIGGER_NEGEDGE 3
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#define STARFIVE_INTC_NUM 2
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#define STARFIVE_INTC_SRC_IRQ_NUM 32
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#define STARFIVE_INTC_TYPE_NUM 16
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struct starfive_irq_chip {
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void __iomem *base;
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struct irq_domain *domain;
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raw_spinlock_t lock;
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};
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static void starfive_intc_mod(struct starfive_irq_chip *irqc, u32 reg, u32 mask, u32 data)
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{
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u32 value;
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value = ioread32(irqc->base + reg) & ~mask;
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data &= mask;
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data |= value;
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iowrite32(data, irqc->base + reg);
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}
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static void starfive_intc_bit_set(struct starfive_irq_chip *irqc,
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u32 reg, u32 bit_mask)
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{
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u32 value;
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value = ioread32(irqc->base + reg);
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value |= bit_mask;
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iowrite32(value, irqc->base + reg);
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}
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static void starfive_intc_bit_clear(struct starfive_irq_chip *irqc,
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u32 reg, u32 bit_mask)
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{
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u32 value;
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value = ioread32(irqc->base + reg);
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value &= ~bit_mask;
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iowrite32(value, irqc->base + reg);
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}
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static void starfive_intc_unmask(struct irq_data *d)
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{
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struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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int i, bitpos;
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i = d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM;
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bitpos = d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM;
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guard(raw_spinlock)(&irqc->lock);
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starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos));
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}
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static void starfive_intc_mask(struct irq_data *d)
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{
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struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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int i, bitpos;
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i = d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM;
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bitpos = d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM;
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guard(raw_spinlock)(&irqc->lock);
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starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_MASK(i), BIT(bitpos));
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}
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static void starfive_intc_ack(struct irq_data *d)
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{
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/* for handle_edge_irq, nothing to do */
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}
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static int starfive_intc_set_type(struct irq_data *d, unsigned int type)
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{
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struct starfive_irq_chip *irqc = irq_data_get_irq_chip_data(d);
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u32 i, bitpos, ty_pos, ty_shift, trigger, typeval;
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irq_flow_handler_t handler;
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i = d->hwirq / STARFIVE_INTC_SRC_IRQ_NUM;
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bitpos = d->hwirq % STARFIVE_INTC_SRC_IRQ_NUM;
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ty_pos = bitpos / STARFIVE_INTC_TYPE_NUM;
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ty_shift = (bitpos % STARFIVE_INTC_TYPE_NUM) * 2;
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switch (type) {
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case IRQF_TRIGGER_LOW:
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trigger = STARFIVE_INTC_TRIGGER_LOW;
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handler = handle_level_irq;
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break;
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case IRQF_TRIGGER_HIGH:
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trigger = STARFIVE_INTC_TRIGGER_HIGH;
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handler = handle_level_irq;
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break;
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case IRQF_TRIGGER_FALLING:
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trigger = STARFIVE_INTC_TRIGGER_NEGEDGE;
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handler = handle_edge_irq;
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break;
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case IRQF_TRIGGER_RISING:
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trigger = STARFIVE_INTC_TRIGGER_POSEDGE;
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handler = handle_edge_irq;
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break;
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default:
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return -EINVAL;
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}
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irq_set_handler_locked(d, handler);
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typeval = trigger << ty_shift;
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guard(raw_spinlock)(&irqc->lock);
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starfive_intc_mod(irqc, STARFIVE_INTC_SRC_TYPE(i) + 4 * ty_pos,
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STARFIVE_INTC_TRIGGER_MASK << ty_shift, typeval);
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/* Once the type is updated, clear interrupt can help to reset the type value */
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starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos));
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starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(bitpos));
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return 0;
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}
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static struct irq_chip intc_dev = {
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.name = "StarFive JHB100 INTC",
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.irq_unmask = starfive_intc_unmask,
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.irq_mask = starfive_intc_mask,
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.irq_ack = starfive_intc_ack,
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.irq_set_type = starfive_intc_set_type,
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};
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static int starfive_intc_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_domain_set_info(d, irq, hwirq, &intc_dev, d->host_data,
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handle_level_irq, NULL, NULL);
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return 0;
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}
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static const struct irq_domain_ops starfive_intc_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = starfive_intc_map,
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};
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static void starfive_intc_irq_handler(struct irq_desc *desc)
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{
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struct starfive_irq_chip *irqc = irq_data_get_irq_handler_data(&desc->irq_data);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long value;
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int hwirq;
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chained_irq_enter(chip, desc);
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for (int i = 0; i < STARFIVE_INTC_NUM; i++) {
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value = ioread32(irqc->base + STARFIVE_INTC_SRC_INT(i));
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while (value) {
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hwirq = ffs(value) - 1;
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generic_handle_domain_irq(irqc->domain,
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hwirq + i * STARFIVE_INTC_SRC_IRQ_NUM);
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starfive_intc_bit_set(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(hwirq));
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starfive_intc_bit_clear(irqc, STARFIVE_INTC_SRC_CLEAR(i), BIT(hwirq));
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__clear_bit(hwirq, &value);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static int starfive_intc_probe(struct platform_device *pdev, struct device_node *parent)
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{
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struct device_node *intc = pdev->dev.of_node;
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struct reset_control *rst;
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struct clk *clk;
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int parent_irq;
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struct starfive_irq_chip *irqc __free(kfree) = kzalloc_obj(*irqc);
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if (!irqc)
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return -ENOMEM;
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irqc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(irqc->base))
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return dev_err_probe(&pdev->dev, PTR_ERR(irqc->base), "unable to map registers\n");
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rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL);
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if (IS_ERR(rst))
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return dev_err_probe(&pdev->dev, PTR_ERR(rst),
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"Unable to get and deassert reset control\n");
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clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Unable to get and enable clock\n");
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raw_spin_lock_init(&irqc->lock);
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irqc->domain = irq_domain_create_linear(of_fwnode_handle(intc),
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STARFIVE_INTC_SRC_IRQ_NUM * STARFIVE_INTC_NUM,
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&starfive_intc_domain_ops, irqc);
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if (!irqc->domain)
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return dev_err_probe(&pdev->dev, -EINVAL, "Unable to create IRQ domain\n");
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parent_irq = of_irq_get(intc, 0);
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if (parent_irq < 0) {
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irq_domain_remove(irqc->domain);
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return dev_err_probe(&pdev->dev, parent_irq, "Failed to get main IRQ\n");
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}
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irq_set_chained_handler_and_data(parent_irq, starfive_intc_irq_handler,
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irqc);
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dev_info(&pdev->dev, "Interrupt controller register, nr_irqs %d\n",
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STARFIVE_INTC_SRC_IRQ_NUM * STARFIVE_INTC_NUM);
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retain_and_null_ptr(irqc);
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return 0;
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}
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IRQCHIP_PLATFORM_DRIVER_BEGIN(starfive_intc)
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IRQCHIP_MATCH("starfive,jhb100-intc", starfive_intc_probe)
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IRQCHIP_PLATFORM_DRIVER_END(starfive_intc)
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MODULE_DESCRIPTION("StarFive JHB100 External Interrupt Controller");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
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