137 lines
4.9 KiB
C
137 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _HWS_PCIE_REG_H
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#define _HWS_PCIE_REG_H
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#include <linux/bits.h>
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#include <linux/sizes.h>
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#define XDMA_CHANNEL_NUM_MAX (1)
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#define MAX_NUM_ENGINES (XDMA_CHANNEL_NUM_MAX * 2)
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#define PCIE_BARADDROFSIZE 4u
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#define PCI_BUS_ACCESS_BASE 0x00000000U
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#define INT_EN_REG_BASE (PCI_BUS_ACCESS_BASE + 0x0134U)
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#define PCIEBR_EN_REG_BASE (PCI_BUS_ACCESS_BASE + 0x0148U)
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#define PCIE_INT_DEC_REG_BASE (PCI_BUS_ACCESS_BASE + 0x0138U)
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#define HWS_INT_EN_MASK 0x0003FFFFU
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#define PCIEBAR_AXI_BASE 0x20000000U
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#define CTL_REG_ACC_BASE 0x0
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#define PCI_ADDR_TABLE_BASE CTL_REG_ACC_BASE
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#define CVBS_IN_BASE 0x00004000U
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#define CVBS_IN_BUF_BASE (CVBS_IN_BASE + (16U * PCIE_BARADDROFSIZE))
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#define CVBS_IN_BUF_BASE2 (CVBS_IN_BASE + (50U * PCIE_BARADDROFSIZE))
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/* 2 Mib */
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#define MAX_L_VIDEO_SIZE 0x200000U
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#define PCI_E_BAR_PAGE_SIZE 0x20000000
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#define PCI_E_BAR_ADD_MASK 0xE0000000
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#define PCI_E_BAR_ADD_LOWMASK 0x1FFFFFFF
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#define MAX_VID_CHANNELS 4
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#define MAX_MM_VIDEO_SIZE SZ_4M
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#define MAX_VIDEO_HW_W 1920
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#define MAX_VIDEO_HW_H 1080
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#define MAX_VIDEO_SCALER_SIZE (1920U * 1080U * 2U)
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#define MIN_VAMP_BRIGHTNESS_UNITS 0
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#define MAX_VAMP_BRIGHTNESS_UNITS 0xff
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#define MIN_VAMP_CONTRAST_UNITS 0
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#define MAX_VAMP_CONTRAST_UNITS 0xff
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#define MIN_VAMP_SATURATION_UNITS 0
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#define MAX_VAMP_SATURATION_UNITS 0xff
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#define MIN_VAMP_HUE_UNITS 0
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#define MAX_VAMP_HUE_UNITS 0xff
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#define HWS_BRIGHTNESS_DEFAULT 0x80
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#define HWS_CONTRAST_DEFAULT 0x80
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#define HWS_SATURATION_DEFAULT 0x80
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#define HWS_HUE_DEFAULT 0x00
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/* Core/global status. */
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#define HWS_REG_SYS_STATUS (CVBS_IN_BASE + 0 * PCIE_BARADDROFSIZE)
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/* bit3: DMA busy, bit2: int, ... */
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#define HWS_SYS_DMA_BUSY_BIT BIT(3) /* 0x08 = DMA busy flag */
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#define HWS_REG_DEC_MODE (CVBS_IN_BASE + 0 * PCIE_BARADDROFSIZE)
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/* Main control register */
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#define HWS_REG_CTL (CVBS_IN_BASE + 4 * PCIE_BARADDROFSIZE)
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#define HWS_CTL_IRQ_ENABLE_BIT BIT(0) /* Global interrupt enable bit */
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/* Write 0x00 to fully reset decoder,
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* set bit 31=1 to "start run",
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* low byte=0x13 selects YUYV/BT.709/etc,
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* in ReadChipId() we also write 0x00 and 0x10 here for chip-ID sequencing.
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*/
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/* Per-channel done flags. */
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#define HWS_REG_INT_STATUS (CVBS_IN_BASE + 1 * PCIE_BARADDROFSIZE)
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#define HWS_SYS_BUSY_BIT BIT(2) /* matches old 0x04 test */
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/* Capture enable switches. */
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/* bit0-3: CH0-CH3 video enable */
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#define HWS_REG_VCAP_ENABLE (CVBS_IN_BASE + 2 * PCIE_BARADDROFSIZE)
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/* bits0-3: signal present, bits8-11: interlace */
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#define HWS_REG_ACTIVE_STATUS (CVBS_IN_BASE + 5 * PCIE_BARADDROFSIZE)
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/* bits0-3: HDCP detected */
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#define HWS_REG_HDCP_STATUS (CVBS_IN_BASE + 8 * PCIE_BARADDROFSIZE)
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#define HWS_REG_DMA_MAX_SIZE (CVBS_IN_BASE + 9 * PCIE_BARADDROFSIZE)
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/* Buffer addresses (written once during init/reset). */
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/* Base of host-visible buffer. */
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#define HWS_REG_VBUF1_ADDR (CVBS_IN_BASE + 25 * PCIE_BARADDROFSIZE)
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/* Per-channel DMA address. */
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#define HWS_REG_DMA_ADDR(ch) (CVBS_IN_BASE + (26 + (ch)) * PCIE_BARADDROFSIZE)
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/* Per-channel live buffer toggles (read-only). */
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#define HWS_REG_VBUF_TOGGLE(ch) (CVBS_IN_BASE + (32 + (ch)) * PCIE_BARADDROFSIZE)
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/*
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* Returns 0 or 1 = which half of the video ring the DMA engine is
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* currently filling for channel *ch* (0-3).
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*/
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/* Per-interrupt bits (video 0-3). */
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#define HWS_INT_VDONE_BIT(ch) BIT(ch) /* 0x01,0x02,0x04,0x08 */
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#define HWS_REG_INT_ACK (CVBS_IN_BASE + 0x4000 + 1 * PCIE_BARADDROFSIZE)
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/* 16-bit W | 16-bit H. */
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#define HWS_REG_IN_RES(ch) (CVBS_IN_BASE + (90 + (ch) * 2) * PCIE_BARADDROFSIZE)
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/* B|C|H|S packed bytes. */
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#define HWS_REG_BCHS(ch) (CVBS_IN_BASE + (91 + (ch) * 2) * PCIE_BARADDROFSIZE)
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/* Input fps. */
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#define HWS_REG_FRAME_RATE(ch) (CVBS_IN_BASE + (110 + (ch)) * PCIE_BARADDROFSIZE)
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/* Programmed out W|H. */
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#define HWS_REG_OUT_RES(ch) (CVBS_IN_BASE + (120 + (ch)) * PCIE_BARADDROFSIZE)
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/* Programmed out fps. */
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#define HWS_REG_OUT_FRAME_RATE(ch) (CVBS_IN_BASE + (130 + (ch)) * PCIE_BARADDROFSIZE)
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/* Device version/port ID/subversion register. */
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#define HWS_REG_DEVICE_INFO (CVBS_IN_BASE + 88 * PCIE_BARADDROFSIZE)
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/*
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* Reading this 32-bit word returns:
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* bits 7:0 = "device version"
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* bits 15:8 = "device sub-version"
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* bits 23:24 = "HW key / port ID" etc.
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* bits 31:28 = "support YV12" flags
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*/
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/* Convenience aliases for individual channels. */
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#define HWS_REG_VBUF_TOGGLE_CH0 HWS_REG_VBUF_TOGGLE(0)
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#define HWS_REG_VBUF_TOGGLE_CH1 HWS_REG_VBUF_TOGGLE(1)
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#define HWS_REG_VBUF_TOGGLE_CH2 HWS_REG_VBUF_TOGGLE(2)
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#define HWS_REG_VBUF_TOGGLE_CH3 HWS_REG_VBUF_TOGGLE(3)
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#endif /* _HWS_PCIE_REG_H */
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