385 lines
12 KiB
C
385 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module 340 (TFE)
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*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/delay.h>
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#include <linux/bitfield.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include "camss.h"
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#include "camss-vfe.h"
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#define TFE_GLOBAL_RESET_CMD (0x014)
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#define TFE_GLOBAL_RESET_CMD_CORE BIT(0)
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#define TFE_REG_UPDATE_CMD (0x02c)
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#define TFE_IRQ_CMD (0x030)
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#define TFE_IRQ_CMD_CLEAR BIT(0)
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#define TFE_IRQ_MASK_0 (0x034)
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#define TFE_IRQ_MASK_0_RST_DONE BIT(0)
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#define TFE_IRQ_MASK_0_BUS_WR BIT(1)
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#define TFE_IRQ_MASK_1 (0x038)
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#define TFE_IRQ_MASK_2 (0x03c)
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#define TFE_IRQ_CLEAR_0 (0x040)
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#define TFE_IRQ_STATUS_0 (0x04c)
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#define BUS_REG(a) (0xa00 + (a))
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#define TFE_BUS_IRQ_MASK_0 BUS_REG(0x18)
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#define TFE_BUS_IRQ_MASK_RUP_DONE_MASK GENMASK(3, 0)
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#define TFE_BUS_IRQ_MASK_RUP_DONE(sc) FIELD_PREP(TFE_BUS_IRQ_MASK_RUP_DONE_MASK, BIT(sc))
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#define TFE_BUS_IRQ_MASK_BUF_DONE_MASK GENMASK(15, 8)
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#define TFE_BUS_IRQ_MASK_BUF_DONE(sg) FIELD_PREP(TFE_BUS_IRQ_MASK_BUF_DONE_MASK, BIT(sg))
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#define TFE_BUS_IRQ_MASK_0_CONS_VIOL BIT(28)
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#define TFE_BUS_IRQ_MASK_0_VIOL BIT(30)
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#define TFE_BUS_IRQ_MASK_0_IMG_VIOL BIT(31)
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#define TFE_BUS_IRQ_MASK_1 BUS_REG(0x1c)
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#define TFE_BUS_IRQ_CLEAR_0 BUS_REG(0x20)
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#define TFE_BUS_IRQ_STATUS_0 BUS_REG(0x28)
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#define TFE_BUS_IRQ_CMD BUS_REG(0x30)
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#define TFE_BUS_IRQ_CMD_CLEAR BIT(0)
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#define TFE_BUS_STATUS_CLEAR BUS_REG(0x60)
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#define TFE_BUS_VIOLATION_STATUS BUS_REG(0x64)
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#define TFE_BUS_OVERFLOW_STATUS BUS_REG(0x68)
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#define TFE_BUS_IMAGE_SZ_VIOLATION_STATUS BUS_REG(0x70)
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#define TFE_BUS_CLIENT_CFG(c) BUS_REG(0x200 + (c) * 0x100)
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#define TFE_BUS_CLIENT_CFG_EN BIT(0)
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#define TFE_BUS_CLIENT_CFG_AUTORECOVER BIT(4)
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#define TFE_BUS_CLIENT_CFG_MODE_FRAME BIT(16)
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#define TFE_BUS_IMAGE_ADDR(c) BUS_REG(0x204 + (c) * 0x100)
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#define TFE_BUS_FRAME_INCR(c) BUS_REG(0x208 + (c) * 0x100)
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#define TFE_BUS_IMAGE_CFG_0(c) BUS_REG(0x20c + (c) * 0x100)
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#define TFE_BUS_IMAGE_CFG_0_DEFAULT 0xffff
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#define TFE_BUS_IMAGE_CFG_1(c) BUS_REG(0x210 + (c) * 0x100)
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#define TFE_BUS_IMAGE_CFG_2(c) BUS_REG(0x214 + (c) * 0x100)
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#define TFE_BUS_IMAGE_CFG_2_DEFAULT 0xffff
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#define TFE_BUS_PACKER_CFG(c) BUS_REG(0x218 + (c) * 0x100)
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#define TFE_BUS_PACKER_CFG_FMT_PLAIN8 0x1
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#define TFE_BUS_PACKER_CFG_FMT_PLAIN64 0xa
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#define TFE_BUS_PACKER_CFG_FMT_MIPI10 0xc
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#define TFE_BUS_PACKER_CFG_FMT_MIPI12 0xd
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#define TFE_BUS_IRQ_SUBSAMPLE_CFG_0(c) BUS_REG(0x230 + (c) * 0x100)
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#define TFE_BUS_IRQ_SUBSAMPLE_CFG_1(c) BUS_REG(0x234 + (c) * 0x100)
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#define TFE_BUS_FRAMEDROP_CFG_0(c) BUS_REG(0x238 + (c) * 0x100)
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#define TFE_BUS_FRAMEDROP_CFG_1(c) BUS_REG(0x23c + (c) * 0x100)
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#define PP_CROP_REG(a) (0x2800 + (a))
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#define TFE_PP_CROP_CFG PP_CROP_REG(0x60)
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#define TFE_PP_CROP_CFG_EN (BIT(0) | BIT(9))
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#define TFE_PP_CROP_LINE_CFG PP_CROP_REG(0x68)
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#define TFE_PP_CROP_FIRST GENMASK(29, 16)
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#define TFE_PP_CROP_LAST GENMASK(13, 0)
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#define TFE_PP_CROP_PIX_CFG PP_CROP_REG(0x6C)
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enum tfe_client {
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TFE_CLI_BAYER,
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TFE_CLI_IDEAL_RAW,
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TFE_CLI_STATS_TINTLESS_BG,
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TFE_CLI_STATS_BHIST,
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TFE_CLI_STATS_AWB_BG,
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TFE_CLI_STATS_AEC_BG,
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TFE_CLI_STATS_BAF,
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TFE_CLI_RDI0,
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TFE_CLI_RDI1,
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TFE_CLI_RDI2,
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TFE_CLI_NUM
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};
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enum tfe_iface {
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TFE_IFACE_PIX,
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TFE_IFACE_RDI0,
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TFE_IFACE_RDI1,
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TFE_IFACE_RDI2,
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TFE_IFACE_NUM
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};
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enum tfe_subgroups {
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TFE_SUBGROUP_BAYER,
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TFE_SUBGROUP_IDEAL_RAW,
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TFE_SUBGROUP_HDR,
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TFE_SUBGROUP_BG,
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TFE_SUBGROUP_BAF,
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TFE_SUBGROUP_RDI0,
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TFE_SUBGROUP_RDI1,
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TFE_SUBGROUP_RDI2,
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TFE_SUBGROUP_NUM
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};
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static enum tfe_client tfe_wm_client_map[VFE_LINE_NUM_MAX] = {
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[VFE_LINE_RDI0] = TFE_CLI_RDI0,
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[VFE_LINE_RDI1] = TFE_CLI_RDI1,
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[VFE_LINE_RDI2] = TFE_CLI_RDI2,
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[VFE_LINE_PIX] = TFE_CLI_BAYER,
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};
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static enum tfe_iface tfe_line_iface_map[VFE_LINE_NUM_MAX] = {
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[VFE_LINE_RDI0] = TFE_IFACE_RDI0,
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[VFE_LINE_RDI1] = TFE_IFACE_RDI1,
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[VFE_LINE_RDI2] = TFE_IFACE_RDI2,
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[VFE_LINE_PIX] = TFE_IFACE_PIX,
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};
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static enum vfe_line_id tfe_subgroup_line_map[TFE_SUBGROUP_NUM] = {
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[TFE_SUBGROUP_BAYER] = VFE_LINE_PIX,
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[TFE_SUBGROUP_IDEAL_RAW] = VFE_LINE_PIX,
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[TFE_SUBGROUP_HDR] = VFE_LINE_PIX,
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[TFE_SUBGROUP_BG] = VFE_LINE_PIX,
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[TFE_SUBGROUP_BAF] = VFE_LINE_PIX,
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[TFE_SUBGROUP_RDI0] = VFE_LINE_RDI0,
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[TFE_SUBGROUP_RDI1] = VFE_LINE_RDI1,
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[TFE_SUBGROUP_RDI2] = VFE_LINE_RDI2,
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};
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static inline enum tfe_iface __line_to_iface(enum vfe_line_id line_id)
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{
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if (line_id <= VFE_LINE_NONE || line_id >= VFE_LINE_NUM_MAX) {
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pr_warn("VFE: Invalid line %d\n", line_id);
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return TFE_IFACE_RDI0;
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}
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return tfe_line_iface_map[line_id];
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}
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static inline enum vfe_line_id __iface_to_line(unsigned int iface)
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{
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int i;
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for (i = 0; i < VFE_LINE_NUM_MAX; i++) {
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if (tfe_line_iface_map[i] == iface)
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return i;
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}
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return VFE_LINE_NONE;
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}
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static inline enum vfe_line_id __subgroup_to_line(enum tfe_subgroups sg)
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{
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if (sg >= TFE_SUBGROUP_NUM)
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return VFE_LINE_NONE;
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return tfe_subgroup_line_map[sg];
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}
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static void vfe_global_reset(struct vfe_device *vfe)
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{
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writel(TFE_IRQ_MASK_0_RST_DONE, vfe->base + TFE_IRQ_MASK_0);
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writel(TFE_GLOBAL_RESET_CMD_CORE, vfe->base + TFE_GLOBAL_RESET_CMD);
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}
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static irqreturn_t vfe_isr(int irq, void *dev)
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{
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struct vfe_device *vfe = dev;
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u32 status;
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int i;
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status = readl_relaxed(vfe->base + TFE_IRQ_STATUS_0);
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writel_relaxed(status, vfe->base + TFE_IRQ_CLEAR_0);
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writel_relaxed(TFE_IRQ_CMD_CLEAR, vfe->base + TFE_IRQ_CMD);
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if (status & TFE_IRQ_MASK_0_RST_DONE) {
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dev_dbg(vfe->camss->dev, "VFE%u: Reset done!", vfe->id);
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vfe_isr_reset_ack(vfe);
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}
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if (status & TFE_IRQ_MASK_0_BUS_WR) {
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u32 bus_status = readl_relaxed(vfe->base + TFE_BUS_IRQ_STATUS_0);
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writel_relaxed(bus_status, vfe->base + TFE_BUS_IRQ_CLEAR_0);
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writel_relaxed(TFE_BUS_IRQ_CMD_CLEAR, vfe->base + TFE_BUS_IRQ_CMD);
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for (i = 0; i < TFE_IFACE_NUM; i++) {
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if (bus_status & TFE_BUS_IRQ_MASK_RUP_DONE(i))
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vfe->res->hw_ops->reg_update_clear(vfe, __iface_to_line(i));
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}
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for (i = 0; i < TFE_SUBGROUP_NUM; i++) {
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if (bus_status & TFE_BUS_IRQ_MASK_BUF_DONE(i))
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vfe_buf_done(vfe, __subgroup_to_line(i));
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}
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if (bus_status & TFE_BUS_IRQ_MASK_0_CONS_VIOL)
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dev_err_ratelimited(vfe->camss->dev, "VFE%u: Bad config violation",
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vfe->id);
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if (bus_status & TFE_BUS_IRQ_MASK_0_VIOL)
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dev_err_ratelimited(vfe->camss->dev, "VFE%u: Input data violation",
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vfe->id);
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if (bus_status & TFE_BUS_IRQ_MASK_0_IMG_VIOL)
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dev_err_ratelimited(vfe->camss->dev, "VFE%u: Image size violation",
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vfe->id);
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}
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status = readl_relaxed(vfe->base + TFE_BUS_OVERFLOW_STATUS);
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if (status) {
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writel_relaxed(status, vfe->base + TFE_BUS_STATUS_CLEAR);
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for (i = 0; i < TFE_CLI_NUM; i++) {
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if (status & BIT(i))
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dev_err_ratelimited(vfe->camss->dev,
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"VFE%u: bus overflow for client %u\n",
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vfe->id, i);
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}
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}
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return IRQ_HANDLED;
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}
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static int vfe_halt(struct vfe_device *vfe)
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{
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/* rely on vfe_disable_output() to stop the VFE */
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return 0;
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}
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static void vfe_enable_irq(struct vfe_device *vfe)
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{
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writel(TFE_IRQ_MASK_0_RST_DONE | TFE_IRQ_MASK_0_BUS_WR,
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vfe->base + TFE_IRQ_MASK_0);
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writel(TFE_BUS_IRQ_MASK_RUP_DONE_MASK | TFE_BUS_IRQ_MASK_BUF_DONE_MASK |
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TFE_BUS_IRQ_MASK_0_CONS_VIOL | TFE_BUS_IRQ_MASK_0_VIOL |
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TFE_BUS_IRQ_MASK_0_IMG_VIOL, vfe->base + TFE_BUS_IRQ_MASK_0);
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}
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static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
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struct vfe_line *line)
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{
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u8 client = tfe_wm_client_map[wm];
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writel_relaxed(addr, vfe->base + TFE_BUS_IMAGE_ADDR(client));
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}
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static u32 vfe_packer_format(struct vfe_device *vfe, u32 pixelformat)
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{
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const struct camss_formats *fmt = vfe->res->formats_rdi;
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unsigned int bpp = 0;
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int i;
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for (i = 0; i < fmt->nformats; i++) {
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if (fmt->formats[i].pixelformat == pixelformat) {
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bpp = fmt->formats[i].mbus_bpp;
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break;
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}
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}
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switch (bpp) {
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case 10:
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return TFE_BUS_PACKER_CFG_FMT_MIPI10;
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case 12:
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return TFE_BUS_PACKER_CFG_FMT_MIPI12;
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default:
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return TFE_BUS_PACKER_CFG_FMT_PLAIN8;
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}
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}
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static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
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{
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struct v4l2_pix_format_mplane *pix = &line->video_out.active_fmt.fmt.pix_mp;
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u32 stride = pix->plane_fmt[0].bytesperline;
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u8 client = tfe_wm_client_map[wm];
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u32 cfg = TFE_BUS_CLIENT_CFG_EN;
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if (client == TFE_CLI_BAYER) { /* PIX - Line based */
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struct v4l2_rect *crop = &line->crop;
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/* Cropping */
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writel_relaxed(TFE_PP_CROP_CFG_EN, vfe->base + TFE_PP_CROP_CFG);
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writel_relaxed(FIELD_PREP(TFE_PP_CROP_FIRST, crop->top) |
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FIELD_PREP(TFE_PP_CROP_LAST, crop->top + crop->height - 1),
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vfe->base + TFE_PP_CROP_LINE_CFG);
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writel_relaxed(FIELD_PREP(TFE_PP_CROP_FIRST, crop->left) |
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FIELD_PREP(TFE_PP_CROP_LAST, crop->left + crop->width - 1),
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vfe->base + TFE_PP_CROP_PIX_CFG);
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/* Write Engine */
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writel_relaxed(pix->width | (pix->height << 16),
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vfe->base + TFE_BUS_IMAGE_CFG_0(client));
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writel_relaxed(0u, vfe->base + TFE_BUS_IMAGE_CFG_1(client));
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writel_relaxed(stride, vfe->base + TFE_BUS_IMAGE_CFG_2(client));
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writel_relaxed(stride * pix->height, vfe->base + TFE_BUS_FRAME_INCR(client));
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writel_relaxed(vfe_packer_format(vfe, pix->pixelformat),
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vfe->base + TFE_BUS_PACKER_CFG(client));
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cfg |= TFE_BUS_CLIENT_CFG_AUTORECOVER;
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} else { /* RDI - Frame based */
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writel_relaxed(TFE_BUS_IMAGE_CFG_0_DEFAULT,
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vfe->base + TFE_BUS_IMAGE_CFG_0(client));
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writel_relaxed(0u, vfe->base + TFE_BUS_IMAGE_CFG_1(client));
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writel_relaxed(TFE_BUS_IMAGE_CFG_2_DEFAULT,
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vfe->base + TFE_BUS_IMAGE_CFG_2(client));
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writel_relaxed(stride * pix->height, vfe->base + TFE_BUS_FRAME_INCR(client));
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writel_relaxed(TFE_BUS_PACKER_CFG_FMT_PLAIN64,
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vfe->base + TFE_BUS_PACKER_CFG(client));
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cfg |= TFE_BUS_CLIENT_CFG_MODE_FRAME;
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}
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/* No dropped frames, one irq per frame */
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writel_relaxed(0, vfe->base + TFE_BUS_FRAMEDROP_CFG_0(client));
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writel_relaxed(1, vfe->base + TFE_BUS_FRAMEDROP_CFG_1(client));
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writel_relaxed(0, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_0(client));
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writel_relaxed(1, vfe->base + TFE_BUS_IRQ_SUBSAMPLE_CFG_1(client));
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vfe_enable_irq(vfe);
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writel(cfg, vfe->base + TFE_BUS_CLIENT_CFG(client));
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dev_dbg(vfe->camss->dev, "VFE%u: Started client %u width %u height %u stride %u\n",
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vfe->id, client, pix->width, pix->height, stride);
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}
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static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
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{
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u8 client = tfe_wm_client_map[wm];
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writel(0, vfe->base + TFE_BUS_CLIENT_CFG(client));
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dev_dbg(vfe->camss->dev, "VFE%u: Stopped client %u\n", vfe->id, client);
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}
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static const struct camss_video_ops vfe_video_ops_520 = {
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.queue_buffer = vfe_queue_buffer_v2,
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.flush_buffers = vfe_flush_buffers,
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};
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static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
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{
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vfe->video_ops = vfe_video_ops_520;
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}
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static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
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{
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vfe->reg_update |= BIT(__line_to_iface(line_id));
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writel_relaxed(vfe->reg_update, vfe->base + TFE_REG_UPDATE_CMD);
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}
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static void vfe_reg_update_clear(struct vfe_device *vfe, enum vfe_line_id line_id)
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{
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vfe->reg_update &= ~BIT(__line_to_iface(line_id));
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}
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const struct vfe_hw_ops vfe_ops_340 = {
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.global_reset = vfe_global_reset,
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.hw_version = vfe_hw_version,
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.isr = vfe_isr,
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.pm_domain_off = vfe_pm_domain_off,
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.pm_domain_on = vfe_pm_domain_on,
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.subdev_init = vfe_subdev_init,
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.vfe_disable = vfe_disable,
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.vfe_enable = vfe_enable_v2,
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.vfe_halt = vfe_halt,
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.vfe_wm_start = vfe_wm_start,
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.vfe_wm_stop = vfe_wm_stop,
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.vfe_buf_done = vfe_buf_done,
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.vfe_wm_update = vfe_wm_update,
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.reg_update = vfe_reg_update,
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.reg_update_clear = vfe_reg_update_clear,
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};
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