193 lines
5.4 KiB
C
193 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) Pengutronix e.K.
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* Author: Sven Püschel <s.pueschel@pengutronix.de>
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*/
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#ifndef __RGA3_HW_H__
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#define __RGA3_HW_H__
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#include <linux/bits.h>
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#include <linux/types.h>
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#define RGA3_CMDBUF_SIZE 0xb8
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#define RGA3_MIN_WIDTH 128
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#define RGA3_MIN_HEIGHT 128
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#define RGA3_MAX_INPUT_WIDTH (8192 - 16)
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#define RGA3_MAX_INPUT_HEIGHT (8192 - 16)
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#define RGA3_MAX_OUTPUT_WIDTH (8192 - 64)
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#define RGA3_MAX_OUTPUT_HEIGHT (8192 - 64)
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#define RGA3_MAX_SCALING_FACTOR 8
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#define RGA3_RESET_TIMEOUT 1000
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/* Registers address */
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/* sys reg */
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#define RGA3_SYS_CTRL 0x000
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#define RGA3_CMD_CTRL 0x004
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#define RGA3_CMD_ADDR 0x008
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#define RGA3_MI_GROUP_CTRL 0x00c
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#define RGA3_ARQOS_CTRL 0x010
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#define RGA3_VERSION_NUM 0x018
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#define RGA3_VERSION_TIM 0x01c
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#define RGA3_INT_EN 0x020
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#define RGA3_INT_RAW 0x024
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#define RGA3_INT_MSK 0x028
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#define RGA3_INT_CLR 0x02c
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#define RGA3_RO_SRST 0x030
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#define RGA3_STATUS0 0x034
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#define RGA3_SCAN_CNT 0x038
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#define RGA3_CMD_STATE 0x040
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/* cmd reg */
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#define RGA3_WIN0_RD_CTRL 0x100
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#define RGA3_FIRST_CMD_REG RGA3_WIN0_RD_CTRL
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#define RGA3_WIN0_Y_BASE 0x110
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#define RGA3_WIN0_U_BASE 0x114
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#define RGA3_WIN0_V_BASE 0x118
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#define RGA3_WIN0_VIR_STRIDE 0x11c
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#define RGA3_WIN0_FBC_OFF 0x120
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#define RGA3_WIN0_SRC_SIZE 0x124
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#define RGA3_WIN0_ACT_OFF 0x128
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#define RGA3_WIN0_ACT_SIZE 0x12c
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#define RGA3_WIN0_DST_SIZE 0x130
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#define RGA3_WIN0_SCL_FAC 0x134
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#define RGA3_WIN0_UV_VIR_STRIDE 0x138
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#define RGA3_WIN1_RD_CTRL 0x140
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#define RGA3_WIN1_Y_BASE 0x150
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#define RGA3_WIN1_U_BASE 0x154
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#define RGA3_WIN1_V_BASE 0x158
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#define RGA3_WIN1_VIR_STRIDE 0x15c
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#define RGA3_WIN1_FBC_OFF 0x160
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#define RGA3_WIN1_SRC_SIZE 0x164
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#define RGA3_WIN1_ACT_OFF 0x168
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#define RGA3_WIN1_ACT_SIZE 0x16c
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#define RGA3_WIN1_DST_SIZE 0x170
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#define RGA3_WIN1_SCL_FAC 0x174
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#define RGA3_WIN1_UV_VIR_STRIDE 0x178
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#define RGA3_OVLP_CTRL 0x180
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#define RGA3_OVLP_OFF 0x184
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#define RGA3_OVLP_TOP_KEY_MIN 0x188
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#define RGA3_OVLP_TOP_KEY_MAX 0x18c
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#define RGA3_OVLP_TOP_CTRL 0x190
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#define RGA3_OVLP_BOT_CTRL 0x194
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#define RGA3_OVLP_TOP_ALPHA 0x198
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#define RGA3_OVLP_BOT_ALPHA 0x19c
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#define RGA3_WR_CTRL 0x1a0
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#define RGA3_WR_FBCE_CTRL 0x1a4
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#define RGA3_WR_VIR_STRIDE 0x1a8
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#define RGA3_WR_PL_VIR_STRIDE 0x1ac
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#define RGA3_WR_Y_BASE 0x1b0
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#define RGA3_WR_U_BASE 0x1b4
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#define RGA3_WR_V_BASE 0x1b8
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/* Registers value */
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#define RGA3_COLOR_FMT_YUV420 0x0
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#define RGA3_COLOR_FMT_YUV422 0x1
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#define RGA3_COLOR_FMT_YUV420_10B 0x2
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#define RGA3_COLOR_FMT_YUV422_10B 0x3
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/*
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* Use memory ordering names
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* instead of the datasheet naming RGB formats in big endian order
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*/
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#define RGA3_COLOR_FMT_BGR565 0x4
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#define RGA3_COLOR_FMT_BGR888 0x5
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#define RGA3_COLOR_FMT_FIRST_HAS_ALPHA RGA3_COLOR_FMT_BGRA8888
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#define RGA3_COLOR_FMT_BGRA8888 0x6
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#define RGA3_COLOR_FMT_LAST_OUTPUT RGA3_COLOR_FMT_BGRA8888
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/* the following are only supported as inputs */
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#define RGA3_COLOR_FMT_ABGR8888 0x7
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/*
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* the following seem to be unnecessary,
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* as they can be achieved with RB swaps
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*/
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#define RGA3_COLOR_FMT_RGBA8888 0x8
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#define RGA3_COLOR_FMT_ARGB8888 0x9
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#define RGA3_RDWR_FORMAT_SEMI_PLANAR 0x1
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#define RGA3_RDWR_FORMAT_INTERLEAVED 0x2
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#define RGA3_CMD_MODE_MASTER 0x1
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#define RGA3_WIN_CSC_MODE_BT601_L 0x0
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#define RGA3_WIN_CSC_MODE_BT709_L 0x1
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#define RGA3_WIN_CSC_MODE_BT601_F 0x2
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#define RGA3_WIN_CSC_MODE_BT2020_L 0x3
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/* RGA masks */
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/* SYS_CTRL */
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#define RGA3_CCLK_SRESET BIT(4)
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#define RGA3_ACLK_SRESET BIT(3)
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#define RGA3_CMD_MODE BIT(1)
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/* CMD_CTRL */
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#define RGA3_CMD_LINE_START_PULSE BIT(0)
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/* VERSION_NUM */
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#define RGA3_VERSION_NUM_MAJOR GENMASK(31, 28)
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#define RGA3_VERSION_NUM_MINOR GENMASK(27, 20)
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/* INT_* */
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#define RGA3_INT_FRM_DONE BIT(0)
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#define RGA3_INT_DMA_READ_BUS_ERR BIT(2)
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#define RGA3_INT_WIN0_FBC_DEC_ERR BIT(5)
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#define RGA3_INT_WIN0_HOR_ERR BIT(6)
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#define RGA3_INT_WIN0_VER_ERR BIT(7)
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#define RGA3_INT_WR_VER_ERR BIT(13)
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#define RGA3_INT_WR_HOR_ERR BIT(14)
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#define RGA3_INT_WR_BUS_ERR BIT(15)
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#define RGA3_INT_WIN0_IN_FIFO_WR_ERR BIT(16)
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#define RGA3_INT_WIN0_IN_FIFO_RD_ERR BIT(17)
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#define RGA3_INT_WIN0_HOR_FIFO_WR_ERR BIT(18)
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#define RGA3_INT_WIN0_HOR_FIFO_RD_ERR BIT(19)
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#define RGA3_INT_WIN0_VER_FIFO_WR_ERR BIT(20)
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#define RGA3_INT_WIN0_VER_FIFO_RD_ERR BIT(21)
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/* RO_SRST */
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#define RGA3_RO_SRST_DONE GENMASK(5, 0)
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/* *_SIZE */
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#define RGA3_HEIGHT GENMASK(28, 16)
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#define RGA3_WIDTH GENMASK(12, 0)
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/* SCL_FAC */
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#define RGA3_SCALE_VER_FAC GENMASK(31, 16)
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#define RGA3_SCALE_HOR_FAC GENMASK(15, 0)
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/* WINx_CTRL */
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#define RGA3_WIN_CSC_MODE GENMASK(27, 26)
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#define RGA3_WIN_R2Y BIT(25)
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#define RGA3_WIN_Y2R BIT(24)
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#define RGA3_WIN_SCALE_VER_UP BIT(23)
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#define RGA3_WIN_SCALE_VER_BYPASS BIT(22)
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#define RGA3_WIN_SCALE_HOR_UP BIT(21)
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#define RGA3_WIN_SCALE_HOR_BYPASS BIT(20)
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#define RGA3_WIN_YC_SWAP BIT(13)
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#define RGA3_WIN_RBUV_SWAP BIT(12)
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#define RGA3_WIN_RD_FORMAT GENMASK(9, 8)
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#define RGA3_WIN_PIC_FORMAT GENMASK(7, 4)
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#define RGA3_WIN_ENABLE BIT(0)
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/* COLOR_CTRL */
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#define RGA3_OVLP_GLOBAL_ALPHA GENMASK(23, 16)
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#define RGA3_OVLP_COLOR_MODE BIT(0)
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/* ALPHA_CTRL */
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#define RGA3_ALPHA_SELECT_MODE BIT(4)
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#define RGA3_ALPHA_BLEND_MODE GENMASK(3, 2)
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/* WR_CTRL */
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#define RGA3_WR_YC_SWAP BIT(20)
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#define RGA3_WR_SW_OUTSTANDING_MAX GENMASK(18, 13)
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#define RGA3_WR_RBUV_SWAP BIT(12)
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#define RGA3_WR_FORMAT GENMASK(9, 8)
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#define RGA3_WR_PIC_FORMAT GENMASK(7, 4)
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struct rga3_fmt {
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u32 fourcc;
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u8 hw_format;
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bool rbuv_swap;
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bool yc_swap;
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};
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#endif
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