41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2026 Intel Corporation */
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#ifndef _ICE_TXCLK_H_
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#define _ICE_TXCLK_H_
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/**
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* ice_txclk_any_port_uses - check if any port on a PHY uses this TX refclk
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* @ctrl_pf: control PF (owner of the shared tx_refclks map)
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* @phy: PHY index
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* @clk: TX reference clock
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*
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* Return: true if any bit (port) is set for this clock on this PHY
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*/
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static inline bool
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ice_txclk_any_port_uses(const struct ice_pf *ctrl_pf, u8 phy,
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enum ice_e825c_ref_clk clk)
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{
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return find_first_bit(&ctrl_pf->ptp.tx_refclks[phy][clk],
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BITS_PER_LONG) < BITS_PER_LONG;
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}
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static inline enum dpll_lock_status
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ice_txclk_lock_status(enum ice_e825c_ref_clk clk)
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{
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switch (clk) {
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case ICE_REF_CLK_SYNCE:
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case ICE_REF_CLK_EREF0:
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return DPLL_LOCK_STATUS_LOCKED;
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case ICE_REF_CLK_ENET:
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default:
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return DPLL_LOCK_STATUS_UNLOCKED;
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}
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}
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int ice_txclk_set_clk(struct ice_pf *pf, enum ice_e825c_ref_clk clk);
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void ice_txclk_update_and_notify(struct ice_pf *pf);
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struct dpll_pin *ice_txclk_get_pin(struct ice_pf *pf,
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enum ice_e825c_ref_clk ref_clk);
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#endif /* _ICE_TXCLK_H_ */
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