105 lines
2.6 KiB
C
105 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2023 AMD Corporation. All rights reserved. */
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#include <linux/pci.h>
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#include <linux/aer.h>
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#include <linux/bitfield.h>
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#include "../pci.h"
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#include "portdrv.h"
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static bool is_cxl_mem_dev(struct pci_dev *dev)
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{
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/*
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* The capability, status, and control fields in Device 0,
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* Function 0 DVSEC control the CXL functionality of the
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* entire device (CXL 3.0, 8.1.3).
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*/
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if (dev->devfn != PCI_DEVFN(0, 0))
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return false;
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/*
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* CXL Memory Devices must have the 502h class code set (CXL
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* 3.0, 8.1.12.1).
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*/
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if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL)
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return false;
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return true;
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}
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static bool cxl_error_is_native(struct pci_dev *dev)
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{
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struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
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return (pcie_ports_native || host->native_aer);
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}
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static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data)
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{
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struct aer_err_info *info = (struct aer_err_info *)data;
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const struct pci_error_handlers *err_handler;
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if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev))
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return 0;
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guard(device)(&dev->dev);
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err_handler = dev->driver ? dev->driver->err_handler : NULL;
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if (!err_handler)
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return 0;
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if (info->severity == AER_CORRECTABLE) {
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if (err_handler->cor_error_detected)
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err_handler->cor_error_detected(dev);
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} else if (err_handler->error_detected) {
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if (info->severity == AER_NONFATAL)
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err_handler->error_detected(dev, pci_channel_io_normal);
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else if (info->severity == AER_FATAL)
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err_handler->error_detected(dev, pci_channel_io_frozen);
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}
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return 0;
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}
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void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info)
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{
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/*
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* Internal errors of an RCEC indicate an AER error in an
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* RCH's downstream port. Check and handle them in the CXL.mem
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* device driver.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC &&
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is_aer_internal_error(info))
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pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info);
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}
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static int handles_cxl_error_iter(struct pci_dev *dev, void *data)
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{
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bool *handles_cxl = data;
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if (!*handles_cxl)
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*handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev);
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/* Non-zero terminates iteration */
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return *handles_cxl;
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}
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static bool handles_cxl_errors(struct pci_dev *rcec)
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{
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bool handles_cxl = false;
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if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC &&
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pcie_aer_is_native(rcec))
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pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl);
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return handles_cxl;
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}
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void cxl_rch_enable_rcec(struct pci_dev *rcec)
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{
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if (!handles_cxl_errors(rcec))
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return;
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pci_aer_unmask_internal_errors(rcec);
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pci_info(rcec, "CXL: Internal errors unmasked");
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}
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