35 lines
1.4 KiB
C
35 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V8_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V8_H_
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/* Only for QMP V8 PHY - PCIE PCS registers */
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#define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG2 0x00c
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#define QPHY_PCIE_V8_PCS_TX_RX_CONFIG 0x018
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#define QPHY_PCIE_V8_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_PCIE_V8_PCS_OSC_DTCT_ACTIONS 0x090
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#define QPHY_PCIE_V8_PCS_EQ_CONFIG1 0x0a0
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#define QPHY_PCIE_V8_PCS_G3_RXEQEVAL_TIME 0x0f0
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#define QPHY_PCIE_V8_PCS_G4_RXEQEVAL_TIME 0x0f4
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#define QPHY_PCIE_V8_PCS_G4_EQ_CONFIG5 0x108
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#define QPHY_PCIE_V8_PCS_G4_PRE_GAIN 0x15c
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#define QPHY_PCIE_V8_PCS_G12S1_TXDEEMPH_M6DB 0x170
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#define QPHY_PCIE_V8_PCS_G3S2_PRE_GAIN 0x178
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#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG1 0x17c
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#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG3 0x184
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#define QPHY_PCIE_V8_PCS_RX_MARGINING_CONFIG5 0x18c
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#define QPHY_PCIE_V8_PCS_RX_SIGDET_LVL 0x190
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#define QPHY_PCIE_V8_PCS_G3_FOM_EQ_CONFIG5 0x1ac
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#define QPHY_PCIE_V8_PCS_ELECIDLE_DLY_SEL 0x1b8
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#define QPHY_PCIE_V8_PCS_G4_FOM_EQ_CONFIG5 0x1c0
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#define QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6 0x1d0
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#define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG1 0x1dc
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#define QPHY_PCIE_V8_PCS_PCS_TX_RX_CONFIG2 0x1e0
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#define QPHY_PCIE_V8_PCS_EQ_CONFIG4 0x1f8
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#define QPHY_PCIE_V8_PCS_EQ_CONFIG5 0x1fc
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#endif
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