57 lines
1.1 KiB
C
57 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
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*/
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#ifndef __T7_PLL_CLKC_H
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#define __T7_PLL_CLKC_H
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/* GP0 */
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#define CLKID_GP0_PLL_DCO 0
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#define CLKID_GP0_PLL 1
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/* GP1 */
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#define CLKID_GP1_PLL_DCO 0
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#define CLKID_GP1_PLL 1
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/* HIFI */
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#define CLKID_HIFI_PLL_DCO 0
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#define CLKID_HIFI_PLL 1
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/* PCIE */
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#define CLKID_PCIE_PLL_DCO 0
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#define CLKID_PCIE_PLL_DCO_DIV2 1
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#define CLKID_PCIE_PLL_OD 2
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#define CLKID_PCIE_PLL 3
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/* MPLL */
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#define CLKID_MPLL_PREDIV 0
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#define CLKID_MPLL0_DIV 1
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#define CLKID_MPLL0 2
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#define CLKID_MPLL1_DIV 3
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#define CLKID_MPLL1 4
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#define CLKID_MPLL2_DIV 5
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#define CLKID_MPLL2 6
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#define CLKID_MPLL3_DIV 7
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#define CLKID_MPLL3 8
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/* HDMI */
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#define CLKID_HDMI_PLL_DCO 0
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#define CLKID_HDMI_PLL_OD 1
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#define CLKID_HDMI_PLL 2
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/* MCLK */
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#define CLKID_MCLK_PLL_DCO 0
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#define CLKID_MCLK_PRE 1
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#define CLKID_MCLK_PLL 2
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#define CLKID_MCLK_0_SEL 3
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#define CLKID_MCLK_0_DIV2 4
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#define CLKID_MCLK_0_PRE 5
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#define CLKID_MCLK_0 6
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#define CLKID_MCLK_1_SEL 7
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#define CLKID_MCLK_1_DIV2 8
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#define CLKID_MCLK_1_PRE 9
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#define CLKID_MCLK_1 10
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#endif /* __T7_PLL_CLKC_H */
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