221 lines
7.2 KiB
C
221 lines
7.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Kendryte Canaan K230 Clock Drivers
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*
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* Author: Xukai Wang <kingxukai@zohomail.com>
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*/
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#ifndef __DT_BINDINGS_CANAAN_K230_CLOCK_H__
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#define __DT_BINDINGS_CANAAN_K230_CLOCK_H__
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#define K230_CPU0_SRC_GATE 0
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#define K230_CPU0_PLIC_GATE 1
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#define K230_CPU0_NOC_DDRCP4_GATE 2
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#define K230_CPU0_APB_GATE 3
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#define K230_CPU0_SRC_RATE 4
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#define K230_CPU0_AXI_RATE 5
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#define K230_CPU0_PLIC_RATE 6
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#define K230_CPU0_APB_RATE 7
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#define K230_HS_SSI0_MUX 8
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#define K230_HS_USB_REF_MUX 9
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#define K230_HS_HCLK_HIGH_GATE 10
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#define K230_HS_HCLK_GATE 11
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#define K230_HS_SD0_AHB_GATE 12
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#define K230_HS_SD1_AHB_GATE 13
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#define K230_HS_SSI1_AHB_GATE 14
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#define K230_HS_SSI2_AHB_GATE 15
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#define K230_HS_USB0_AHB_GATE 16
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#define K230_HS_USB1_AHB_GATE 17
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#define K230_HS_SSI0_AXI_GATE 18
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#define K230_HS_SSI1_GATE 19
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#define K230_HS_SSI2_GATE 20
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#define K230_HS_QSPI_AXI_SRC_GATE 21
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#define K230_HS_SSI1_AXI_GATE 22
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#define K230_HS_SSI2_AXI_GATE 23
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#define K230_HS_SD_CARD_SRC_GATE 24
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#define K230_HS_SD0_CARD_GATE 25
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#define K230_HS_SD1_CARD_GATE 26
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#define K230_HS_SD_AXI_SRC_GATE 27
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#define K230_HS_SD0_AXI_GATE 28
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#define K230_HS_SD1_AXI_GATE 29
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#define K230_HS_SD0_BASE_GATE 30
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#define K230_HS_SD1_BASE_GATE 31
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#define K230_HS_SSI0_GATE 32
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#define K230_HS_SD_TIMER_SRC_GATE 33
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#define K230_HS_SD0_TIMER_GATE 34
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#define K230_HS_SD1_TIMER_GATE 35
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#define K230_HS_USB0_REF_GATE 36
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#define K230_HS_USB1_REF_GATE 37
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#define K230_HS_HCLK_HIGH_RATE 38
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#define K230_HS_HCLK_RATE 39
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#define K230_HS_SSI0_AXI_RATE 40
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#define K230_HS_SSI1_RATE 41
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#define K230_HS_SSI2_RATE 42
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#define K230_HS_QSPI_AXI_SRC_RATE 43
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#define K230_HS_SD_CARD_SRC_RATE 44
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#define K230_HS_SD_AXI_SRC_RATE 45
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#define K230_HS_USB_REF_50M_RATE 46
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#define K230_HS_SD_TIMER_SRC_RATE 47
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#define K230_TIMER0_MUX 48
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#define K230_TIMER1_MUX 49
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#define K230_TIMER2_MUX 50
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#define K230_TIMER3_MUX 51
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#define K230_TIMER4_MUX 52
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#define K230_TIMER5_MUX 53
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#define K230_SHRM_SRAM_MUX 54
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#define K230_DDRC_SRC_MUX 55
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#define K230_AI_SRC_MUX 56
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#define K230_CAMERA0_MUX 57
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#define K230_CAMERA1_MUX 58
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#define K230_CAMERA2_MUX 59
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#define K230_CPU1_SRC_MUX 60
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#define K230_CPU1_SRC_GATE 61
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#define K230_CPU1_PLIC_GATE 62
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#define K230_CPU1_APB_GATE 63
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#define K230_CPU1_SRC_RATE 64
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#define K230_CPU1_AXI_RATE 65
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#define K230_CPU1_PLIC_RATE 66
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#define K230_PMU_APB_GATE 67
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#define K230_LS_APB_SRC_GATE 68
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#define K230_LS_UART0_APB_GATE 69
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#define K230_LS_UART1_APB_GATE 70
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#define K230_LS_UART2_APB_GATE 71
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#define K230_LS_UART3_APB_GATE 72
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#define K230_LS_UART4_APB_GATE 73
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#define K230_LS_I2C0_APB_GATE 74
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#define K230_LS_I2C1_APB_GATE 75
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#define K230_LS_I2C2_APB_GATE 76
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#define K230_LS_I2C3_APB_GATE 77
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#define K230_LS_I2C4_APB_GATE 78
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#define K230_LS_GPIO_APB_GATE 79
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#define K230_LS_PWM_APB_GATE 80
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#define K230_LS_JAMLINK0_APB_GATE 81
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#define K230_LS_JAMLINK1_APB_GATE 82
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#define K230_LS_JAMLINK2_APB_GATE 83
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#define K230_LS_JAMLINK3_APB_GATE 84
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#define K230_LS_AUDIO_APB_GATE 85
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#define K230_LS_ADC_APB_GATE 86
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#define K230_LS_CODEC_APB_GATE 87
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#define K230_LS_I2C0_GATE 88
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#define K230_LS_I2C1_GATE 89
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#define K230_LS_I2C2_GATE 90
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#define K230_LS_I2C3_GATE 91
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#define K230_LS_I2C4_GATE 92
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#define K230_LS_CODEC_ADC_GATE 93
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#define K230_LS_CODEC_DAC_GATE 94
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#define K230_LS_AUDIO_DEV_GATE 95
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#define K230_LS_PDM_GATE 96
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#define K230_LS_ADC_GATE 97
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#define K230_LS_UART0_GATE 98
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#define K230_LS_UART1_GATE 99
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#define K230_LS_UART2_GATE 100
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#define K230_LS_UART3_GATE 101
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#define K230_LS_UART4_GATE 102
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#define K230_LS_JAMLINK0CO_GATE 103
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#define K230_LS_JAMLINK1CO_GATE 104
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#define K230_LS_JAMLINK2CO_GATE 105
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#define K230_LS_JAMLINK3CO_GATE 106
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#define K230_LS_GPIO_DEBOUNCE_GATE 107
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#define K230_SYSCTL_WDT0_APB_GATE 108
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#define K230_SYSCTL_WDT1_APB_GATE 109
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#define K230_SYSCTL_TIMER_APB_GATE 110
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#define K230_SYSCTL_IOMUX_APB_GATE 111
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#define K230_SYSCTL_MAILBOX_APB_GATE 112
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#define K230_SYSCTL_HDI_GATE 113
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#define K230_SYSCTL_TIME_STAMP_GATE 114
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#define K230_SYSCTL_WDT0_GATE 115
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#define K230_SYSCTL_WDT1_GATE 116
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#define K230_TIMER0_GATE 117
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#define K230_TIMER1_GATE 118
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#define K230_TIMER2_GATE 119
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#define K230_TIMER3_GATE 120
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#define K230_TIMER4_GATE 121
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#define K230_TIMER5_GATE 122
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#define K230_SHRM_APB_GATE 123
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#define K230_SHRM_AXI_GATE 124
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#define K230_SHRM_AXI_SLAVE_GATE 125
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#define K230_SHRM_NONAI2D_AXI_GATE 126
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#define K230_SHRM_SRAM_GATE 127
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#define K230_SHRM_DECOMPRESS_AXI_GATE 128
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#define K230_SHRM_SDMA_AXI_GATE 129
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#define K230_SHRM_PDMA_AXI_GATE 130
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#define K230_DDRC_SRC_GATE 131
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#define K230_DDRC_BYPASS_GATE 132
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#define K230_DDRC_APB_GATE 133
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#define K230_DISPLAY_AHB_GATE 134
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#define K230_DISPLAY_AXI_GATE 135
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#define K230_DISPLAY_GPU_GATE 136
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#define K230_DISPLAY_DPIP_GATE 137
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#define K230_DISPLAY_CFG_GATE 138
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#define K230_DISPLAY_REF_GATE 139
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#define K230_USB_480M_GATE 140
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#define K230_USB_100M_GATE 141
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#define K230_DPHY_DFT_GATE 142
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#define K230_SPI2AXI_GATE 143
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#define K230_AI_SRC_GATE 144
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#define K230_AI_AXI_GATE 145
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#define K230_AI_SRC_RATE 146
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#define K230_CAMERA0_GATE 147
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#define K230_CAMERA1_GATE 148
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#define K230_CAMERA2_GATE 149
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#define K230_LS_APB_SRC_RATE 150
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#define K230_LS_I2C0_RATE 151
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#define K230_LS_I2C1_RATE 152
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#define K230_LS_I2C2_RATE 153
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#define K230_LS_I2C3_RATE 154
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#define K230_LS_I2C4_RATE 155
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#define K230_LS_CODEC_ADC_RATE 156
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#define K230_LS_CODEC_DAC_RATE 157
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#define K230_LS_AUDIO_DEV_RATE 158
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#define K230_LS_PDM_RATE 159
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#define K230_LS_ADC_RATE 160
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#define K230_LS_UART0_RATE 161
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#define K230_LS_UART1_RATE 162
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#define K230_LS_UART2_RATE 163
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#define K230_LS_UART3_RATE 164
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#define K230_LS_UART4_RATE 165
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#define K230_LS_JAMLINKCO_SRC_RATE 166
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#define K230_LS_GPIO_DEBOUNCE_RATE 167
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#define K230_SYSCTL_HDI_RATE 168
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#define K230_SYSCTL_TIME_STAMP_RATE 169
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#define K230_SYSCTL_TEMP_SENSOR_RATE 170
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#define K230_SYSCTL_WDT0_RATE 171
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#define K230_SYSCTL_WDT1_RATE 172
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#define K230_TIMER0_SRC_RATE 173
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#define K230_TIMER1_SRC_RATE 174
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#define K230_TIMER2_SRC_RATE 175
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#define K230_TIMER3_SRC_RATE 176
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#define K230_TIMER4_SRC_RATE 177
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#define K230_TIMER5_SRC_RATE 178
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#define K230_SHRM_APB_RATE 179
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#define K230_DDRC_SRC_RATE 180
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#define K230_DDRC_APB_RATE 181
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#define K230_DISPLAY_AHB_RATE 182
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#define K230_DISPLAY_CLKEXT_RATE 183
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#define K230_DISPLAY_GPU_RATE 184
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#define K230_DISPLAY_DPIP_RATE 185
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#define K230_DISPLAY_CFG_RATE 186
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#define K230_VPU_SRC_GATE 187
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#define K230_VPU_AXI_GATE 188
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#define K230_VPU_DDRCP2_GATE 189
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#define K230_VPU_CFG_GATE 190
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#define K230_VPU_SRC_RATE 191
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#define K230_VPU_AXI_SRC_RATE 192
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#define K230_VPU_CFG_RATE 193
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#define K230_SEC_APB_GATE 194
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#define K230_SEC_FIX_GATE 195
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#define K230_SEC_AXI_GATE 196
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#define K230_SEC_APB_RATE 197
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#define K230_SEC_FIX_RATE 198
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#define K230_SEC_AXI_RATE 199
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#define K230_USB_480M_RATE 200
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#define K230_USB_100M_RATE 201
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#define K230_DPHY_DFT_RATE 202
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#define K230_SPI2AXI_RATE 203
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#define K230_CAMERA0_RATE 204
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#define K230_CAMERA1_RATE 205
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#define K230_CAMERA2_RATE 206
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#define K230_SHRM_SRAM_DIV2 207
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#endif /* __DT_BINDINGS_CANAAN_K230_CLOCK_H__ */
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