127 lines
4.4 KiB
C
127 lines
4.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H
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#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H
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#define GCC_ADSS_PWM_CLK 0
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#define GCC_ADSS_PWM_CLK_SRC 1
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#define GCC_CMN_12GPLL_AHB_CLK 2
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#define GCC_CMN_12GPLL_SYS_CLK 3
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#define GCC_CNOC_LPASS_CFG_CLK 4
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#define GCC_CNOC_PCIE0_1LANE_S_CLK 5
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#define GCC_CNOC_PCIE1_2LANE_S_CLK 6
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#define GCC_CNOC_USB_CLK 7
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#define GCC_GEPHY_SYS_CLK 8
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#define GCC_LPASS_AXIM_CLK_SRC 9
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#define GCC_LPASS_CORE_AXIM_CLK 10
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#define GCC_LPASS_SWAY_CLK 11
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#define GCC_LPASS_SWAY_CLK_SRC 12
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#define GCC_MDIO_AHB_CLK 13
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#define GCC_MDIO_GEPHY_AHB_CLK 14
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#define GCC_NSS_TS_CLK 15
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#define GCC_NSS_TS_CLK_SRC 16
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#define GCC_NSSCC_CLK 17
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#define GCC_NSSCFG_CLK 18
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#define GCC_NSSNOC_ATB_CLK 19
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#define GCC_NSSNOC_MEMNOC_1_CLK 20
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#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21
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#define GCC_NSSNOC_MEMNOC_CLK 22
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#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23
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#define GCC_NSSNOC_NSSCC_CLK 24
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#define GCC_NSSNOC_PCNOC_1_CLK 25
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#define GCC_NSSNOC_QOSGEN_REF_CLK 26
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#define GCC_NSSNOC_SNOC_1_CLK 27
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#define GCC_NSSNOC_SNOC_CLK 28
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#define GCC_NSSNOC_TIMEOUT_REF_CLK 29
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#define GCC_NSSNOC_XO_DCD_CLK 30
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#define GCC_PCIE0_AHB_CLK 31
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#define GCC_PCIE0_AUX_CLK 32
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#define GCC_PCIE0_AXI_M_CLK 33
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#define GCC_PCIE0_AXI_M_CLK_SRC 34
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#define GCC_PCIE0_AXI_S_BRIDGE_CLK 35
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#define GCC_PCIE0_AXI_S_CLK 36
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#define GCC_PCIE0_AXI_S_CLK_SRC 37
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#define GCC_PCIE0_PIPE_CLK 38
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#define GCC_PCIE0_PIPE_CLK_SRC 39
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#define GCC_PCIE0_RCHNG_CLK 40
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#define GCC_PCIE0_RCHNG_CLK_SRC 41
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#define GCC_PCIE1_AHB_CLK 42
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#define GCC_PCIE1_AUX_CLK 43
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#define GCC_PCIE1_AXI_M_CLK 44
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#define GCC_PCIE1_AXI_M_CLK_SRC 45
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#define GCC_PCIE1_AXI_S_BRIDGE_CLK 46
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#define GCC_PCIE1_AXI_S_CLK 47
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#define GCC_PCIE1_AXI_S_CLK_SRC 48
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#define GCC_PCIE1_PIPE_CLK 49
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#define GCC_PCIE1_PIPE_CLK_SRC 50
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#define GCC_PCIE1_RCHNG_CLK 51
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#define GCC_PCIE1_RCHNG_CLK_SRC 52
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#define GCC_PCIE_AUX_CLK_SRC 53
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#define GCC_PCNOC_BFDCD_CLK_SRC 54
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#define GCC_PON_APB_CLK 55
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#define GCC_PON_TM_CLK 56
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#define GCC_PON_TM2X_CLK 57
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#define GCC_PON_TM2X_CLK_SRC 58
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#define GCC_QDSS_AT_CLK 59
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#define GCC_QDSS_AT_CLK_SRC 60
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#define GCC_QDSS_DAP_CLK 61
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#define GCC_QDSS_TSCTR_CLK_SRC 62
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#define GCC_QPIC_AHB_CLK 63
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#define GCC_QPIC_CLK 64
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#define GCC_QPIC_CLK_SRC 65
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#define GCC_QPIC_IO_MACRO_CLK 66
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#define GCC_QPIC_IO_MACRO_CLK_SRC 67
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#define GCC_QRNG_AHB_CLK 68
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#define GCC_QUPV3_AHB_MST_CLK 69
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#define GCC_QUPV3_AHB_SLV_CLK 70
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#define GCC_QUPV3_WRAP_SE0_CLK 71
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#define GCC_QUPV3_WRAP_SE0_CLK_SRC 72
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#define GCC_QUPV3_WRAP_SE1_CLK 73
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#define GCC_QUPV3_WRAP_SE1_CLK_SRC 74
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#define GCC_QUPV3_WRAP_SE2_CLK 75
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#define GCC_QUPV3_WRAP_SE2_CLK_SRC 76
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#define GCC_QUPV3_WRAP_SE3_CLK 77
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#define GCC_QUPV3_WRAP_SE3_CLK_SRC 78
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#define GCC_QUPV3_WRAP_SE4_CLK 79
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#define GCC_QUPV3_WRAP_SE4_CLK_SRC 80
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#define GCC_QUPV3_WRAP_SE5_CLK 81
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#define GCC_QUPV3_WRAP_SE5_CLK_SRC 82
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#define GCC_SDCC1_AHB_CLK 83
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#define GCC_SDCC1_APPS_CLK 84
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#define GCC_SDCC1_APPS_CLK_SRC 85
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#define GCC_SDCC1_ICE_CORE_CLK 86
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 87
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#define GCC_SLEEP_CLK_SRC 88
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#define GCC_SNOC_LPASS_CLK 89
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#define GCC_SNOC_PCIE0_AXI_M_CLK 90
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#define GCC_SNOC_PCIE1_AXI_M_CLK 91
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#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92
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#define GCC_UNIPHY0_AHB_CLK 93
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#define GCC_UNIPHY0_SYS_CLK 94
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#define GCC_UNIPHY1_AHB_CLK 95
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#define GCC_UNIPHY1_SYS_CLK 96
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#define GCC_UNIPHY2_AHB_CLK 97
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#define GCC_UNIPHY2_SYS_CLK 98
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#define GCC_UNIPHY_SYS_CLK_SRC 99
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#define GCC_USB0_AUX_CLK 100
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#define GCC_USB0_AUX_CLK_SRC 101
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#define GCC_USB0_MASTER_CLK 102
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#define GCC_USB0_MASTER_CLK_SRC 103
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#define GCC_USB0_MOCK_UTMI_CLK 104
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#define GCC_USB0_MOCK_UTMI_CLK_SRC 105
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#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106
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#define GCC_USB0_PHY_CFG_AHB_CLK 107
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#define GCC_USB0_PIPE_CLK 108
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#define GCC_USB0_PIPE_CLK_SRC 109
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#define GCC_USB0_SLEEP_CLK 110
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#define GCC_XO_CLK_SRC 111
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#define GPLL0_MAIN 112
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#define GPLL0 113
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#define GPLL2_MAIN 114
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#define GPLL2 115
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#define GPLL4_MAIN 116
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#endif
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