173 lines
6.1 KiB
C
173 lines
6.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
|
/*
|
|
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H
|
|
#define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ9650_H
|
|
|
|
#define GCC_ADSS_PWM_CLK 0
|
|
#define GCC_ADSS_PWM_CLK_SRC 1
|
|
#define GCC_ANOC_PCIE0_1LANE_M_CLK 2
|
|
#define GCC_ANOC_PCIE0_1LANE_S_CLK 3
|
|
#define GCC_ANOC_PCIE1_2LANE_M_CLK 4
|
|
#define GCC_ANOC_PCIE1_2LANE_S_CLK 5
|
|
#define GCC_ANOC_PCIE2_2LANE_M_CLK 6
|
|
#define GCC_ANOC_PCIE2_2LANE_S_CLK 7
|
|
#define GCC_ANOC_PCIE3_2LANE_M_CLK 8
|
|
#define GCC_ANOC_PCIE3_2LANE_S_CLK 9
|
|
#define GCC_ANOC_PCIE4_1LANE_M_CLK 10
|
|
#define GCC_ANOC_PCIE4_1LANE_S_CLK 11
|
|
#define GCC_CMN_12GPLL_AHB_CLK 12
|
|
#define GCC_CMN_12GPLL_APU_CLK 13
|
|
#define GCC_CMN_12GPLL_SYS_CLK 14
|
|
#define GCC_CMN_LDO_CLK 15
|
|
#define GCC_MDIO_AHB_CLK 16
|
|
#define GCC_NSSCC_CLK 17
|
|
#define GCC_NSSCFG_CLK 18
|
|
#define GCC_NSSNOC_ATB_CLK 19
|
|
#define GCC_NSSNOC_MEMNOC_1_CLK 20
|
|
#define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21
|
|
#define GCC_NSSNOC_MEMNOC_CLK 22
|
|
#define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23
|
|
#define GCC_NSSNOC_NSSCC_CLK 24
|
|
#define GCC_NSSNOC_PCNOC_1_CLK 25
|
|
#define GCC_NSSNOC_QOSGEN_REF_CLK 26
|
|
#define GCC_NSSNOC_SNOC_1_CLK 27
|
|
#define GCC_NSSNOC_SNOC_CLK 28
|
|
#define GCC_NSSNOC_TIMEOUT_REF_CLK 29
|
|
#define GCC_NSSNOC_XO_DCD_CLK 30
|
|
#define GCC_NSS_TS_CLK 31
|
|
#define GCC_NSS_TS_CLK_SRC 32
|
|
#define GCC_PCIE0_AHB_CLK 33
|
|
#define GCC_PCIE0_AUX_CLK 34
|
|
#define GCC_PCIE0_AXI_M_CLK 35
|
|
#define GCC_PCIE0_AXI_M_CLK_SRC 36
|
|
#define GCC_PCIE0_AXI_S_BRIDGE_CLK 37
|
|
#define GCC_PCIE0_AXI_S_CLK 38
|
|
#define GCC_PCIE0_AXI_S_CLK_SRC 39
|
|
#define GCC_PCIE0_PIPE_CLK 40
|
|
#define GCC_PCIE0_PIPE_CLK_SRC 41
|
|
#define GCC_PCIE0_RCHNG_CLK 42
|
|
#define GCC_PCIE0_RCHNG_CLK_SRC 43
|
|
#define GCC_PCIE1_AHB_CLK 44
|
|
#define GCC_PCIE1_AUX_CLK 45
|
|
#define GCC_PCIE1_AXI_M_CLK 46
|
|
#define GCC_PCIE1_AXI_M_CLK_SRC 47
|
|
#define GCC_PCIE1_AXI_S_BRIDGE_CLK 48
|
|
#define GCC_PCIE1_AXI_S_CLK 49
|
|
#define GCC_PCIE1_AXI_S_CLK_SRC 50
|
|
#define GCC_PCIE1_PIPE_CLK 51
|
|
#define GCC_PCIE1_PIPE_CLK_SRC 52
|
|
#define GCC_PCIE1_RCHNG_CLK 53
|
|
#define GCC_PCIE1_RCHNG_CLK_SRC 54
|
|
#define GCC_PCIE2_AHB_CLK 55
|
|
#define GCC_PCIE2_AUX_CLK 56
|
|
#define GCC_PCIE2_AXI_M_CLK 57
|
|
#define GCC_PCIE2_AXI_M_CLK_SRC 58
|
|
#define GCC_PCIE2_AXI_S_BRIDGE_CLK 59
|
|
#define GCC_PCIE2_AXI_S_CLK 60
|
|
#define GCC_PCIE2_AXI_S_CLK_SRC 61
|
|
#define GCC_PCIE2_PIPE_CLK 62
|
|
#define GCC_PCIE2_PIPE_CLK_SRC 63
|
|
#define GCC_PCIE2_RCHNG_CLK 64
|
|
#define GCC_PCIE2_RCHNG_CLK_SRC 65
|
|
#define GCC_PCIE3_AHB_CLK 66
|
|
#define GCC_PCIE3_AUX_CLK 67
|
|
#define GCC_PCIE3_AXI_M_CLK 68
|
|
#define GCC_PCIE3_AXI_M_CLK_SRC 69
|
|
#define GCC_PCIE3_AXI_S_BRIDGE_CLK 70
|
|
#define GCC_PCIE3_AXI_S_CLK 71
|
|
#define GCC_PCIE3_AXI_S_CLK_SRC 72
|
|
#define GCC_PCIE3_PIPE_CLK 73
|
|
#define GCC_PCIE3_PIPE_CLK_SRC 74
|
|
#define GCC_PCIE3_RCHNG_CLK 75
|
|
#define GCC_PCIE3_RCHNG_CLK_SRC 76
|
|
#define GCC_PCIE4_AHB_CLK 77
|
|
#define GCC_PCIE4_AUX_CLK 78
|
|
#define GCC_PCIE4_AXI_M_CLK 79
|
|
#define GCC_PCIE4_AXI_M_CLK_SRC 80
|
|
#define GCC_PCIE4_AXI_S_BRIDGE_CLK 81
|
|
#define GCC_PCIE4_AXI_S_CLK 82
|
|
#define GCC_PCIE4_AXI_S_CLK_SRC 83
|
|
#define GCC_PCIE4_PIPE_CLK 84
|
|
#define GCC_PCIE4_PIPE_CLK_SRC 85
|
|
#define GCC_PCIE4_RCHNG_CLK 86
|
|
#define GCC_PCIE4_RCHNG_CLK_SRC 87
|
|
#define GCC_PCIE_AUX_CLK_SRC 88
|
|
#define GCC_PCNOC_BFDCD_CLK_SRC 89
|
|
#define GCC_QDSS_AT_CLK 90
|
|
#define GCC_QDSS_AT_CLK_SRC 91
|
|
#define GCC_QDSS_DAP_CLK 92
|
|
#define GCC_QDSS_TSCTR_CLK_SRC 93
|
|
#define GCC_QPIC_AHB_CLK 94
|
|
#define GCC_QPIC_CLK 95
|
|
#define GCC_QPIC_CLK_SRC 96
|
|
#define GCC_QPIC_IO_MACRO_CLK 97
|
|
#define GCC_QPIC_IO_MACRO_CLK_SRC 98
|
|
#define GCC_QPIC_SLEEP_CLK 99
|
|
#define GCC_QUPV3_2X_CORE_CLK 100
|
|
#define GCC_QUPV3_2X_CORE_CLK_SRC 101
|
|
#define GCC_QUPV3_AHB_MST_CLK 102
|
|
#define GCC_QUPV3_AHB_SLV_CLK 103
|
|
#define GCC_QUPV3_CORE_CLK 104
|
|
#define GCC_QUPV3_SLEEP_CLK 105
|
|
#define GCC_QUPV3_WRAP_SE0_CLK 106
|
|
#define GCC_QUPV3_WRAP_SE0_CLK_SRC 107
|
|
#define GCC_QUPV3_WRAP_SE1_CLK 108
|
|
#define GCC_QUPV3_WRAP_SE1_CLK_SRC 109
|
|
#define GCC_QUPV3_WRAP_SE2_CLK 110
|
|
#define GCC_QUPV3_WRAP_SE2_CLK_SRC 111
|
|
#define GCC_QUPV3_WRAP_SE3_CLK 112
|
|
#define GCC_QUPV3_WRAP_SE3_CLK_SRC 113
|
|
#define GCC_QUPV3_WRAP_SE4_CLK 114
|
|
#define GCC_QUPV3_WRAP_SE4_CLK_SRC 115
|
|
#define GCC_QUPV3_WRAP_SE5_CLK 116
|
|
#define GCC_QUPV3_WRAP_SE5_CLK_SRC 117
|
|
#define GCC_QUPV3_WRAP_SE6_CLK 118
|
|
#define GCC_QUPV3_WRAP_SE6_CLK_SRC 119
|
|
#define GCC_QUPV3_WRAP_SE7_CLK 120
|
|
#define GCC_QUPV3_WRAP_SE7_CLK_SRC 121
|
|
#define GCC_SDCC1_AHB_CLK 122
|
|
#define GCC_SDCC1_APPS_CLK 123
|
|
#define GCC_SDCC1_APPS_CLK_SRC 124
|
|
#define GCC_SDCC1_ICE_CORE_CLK 125
|
|
#define GCC_SDCC1_ICE_CORE_CLK_SRC 126
|
|
#define GCC_SLEEP_CLK_SRC 127
|
|
#define GCC_SNOC_USB_CLK 128
|
|
#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129
|
|
#define GCC_TLMM_AHB_CLK 130
|
|
#define GCC_TLMM_CLK 131
|
|
#define GCC_UNIPHY0_AHB_CLK 132
|
|
#define GCC_UNIPHY0_SYS_CLK 133
|
|
#define GCC_UNIPHY1_AHB_CLK 134
|
|
#define GCC_UNIPHY1_SYS_CLK 135
|
|
#define GCC_UNIPHY2_AHB_CLK 136
|
|
#define GCC_UNIPHY2_SYS_CLK 137
|
|
#define GCC_UNIPHY_SYS_CLK_SRC 138
|
|
#define GCC_USB0_AUX_CLK 139
|
|
#define GCC_USB0_AUX_CLK_SRC 140
|
|
#define GCC_USB0_EUD_AT_CLK 141
|
|
#define GCC_USB0_MASTER_CLK 142
|
|
#define GCC_USB0_MASTER_CLK_SRC 143
|
|
#define GCC_USB0_MOCK_UTMI_CLK 144
|
|
#define GCC_USB0_MOCK_UTMI_CLK_SRC 145
|
|
#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 146
|
|
#define GCC_USB0_PHY_CFG_AHB_CLK 147
|
|
#define GCC_USB0_PIPE_CLK 148
|
|
#define GCC_USB0_PIPE_CLK_SRC 149
|
|
#define GCC_USB0_SLEEP_CLK 150
|
|
#define GCC_USB1_MASTER_CLK 151
|
|
#define GCC_USB1_MOCK_UTMI_CLK 152
|
|
#define GCC_USB1_MOCK_UTMI_CLK_SRC 153
|
|
#define GCC_USB1_MOCK_UTMI_DIV_CLK_SRC 154
|
|
#define GCC_USB1_PHY_CFG_AHB_CLK 155
|
|
#define GCC_USB1_SLEEP_CLK 156
|
|
#define GCC_XO_CLK_SRC 157
|
|
#define GPLL0 158
|
|
#define GPLL0_MAIN 159
|
|
#define GPLL2 160
|
|
#define GPLL2_OUT_MAIN 161
|
|
#define GPLL4 162
|
|
#endif
|